基于重用信息的非易失性缓存动态旁路策略

doi:10.19678/j.issn.1000-3428.0057507

摘要/Abstract

摘要： 非易失性存储器具有能耗低、可扩展性强和存储密度大等优势，可替代传统静态随机存取存储器作为片上缓存，但其写操作的能耗及延迟较高，在大规模应用前需优化写性能。提出一种基于缓存块重用信息的动态旁路策略，用于优化非易失性存储器的缓存性能。分析测试程序访问最后一级缓存（LLC）时的重用特征，根据缓存块的重用信息动态预测相应的写操作是否绕过非易失性缓存，利用预测表进行旁路操作完成LLC缺失时的填充，同时采用动态路径选择进行上级缓存写回操作，通过监控模块为旁路的缓存块选择合适的上级缓存，并将重用计数较高的缓存块填充其中以减少LLC写操作次数。实验结果表明，与未采用旁路策略的缓存设计相比，该策略使4核处理器中所有SPLASH-2程序的运行时间平均减少6.6%，缓存能耗平均降低22.5%，有效提高了整体缓存性能。

关键词: 非易失性存储器, 多核处理器, 缓存, 重用信息, 旁路策略, 能耗

Abstract: Non-Volatile Memory(NVM) has the advantages of low energy consumption,strong scalability and high storage density.It can replace the traditional Static Random Access Memory (SRAM) as on-chip cache,but is also faced with high energy consumption and delay for write operations,so it is necessary to optimize the write performance for large-scale application.This paper proposes a dynamic bypass policy based on cache block reuse information to optimize the cache performance of NVM.It analyzes the reuse characteristics of the test program accessing the Last-Level Cache(LLC).According to the reuse information of the cache block,it dynamically predicts whether the corresponding write operation bypasses the non-volatile cache and completes the filling when LLC is missing using the bypass operation of the prediction table.At the same time,it adopts the dynamic path selection to carry out the upper level cache write back operation,and select the appropriate upper level cache for the bypass cache block through the monitoring module.The cache blocks that are frequently reused are filled into the superior cache to reduce the number of LLC write operations.Experimental results show that the proposed policy can reduce the average running time of all SPLASH-2 programs in a 4-core processor by 6.6% and the average cache energy consumption by 22.5% compared with the cache design without bypass policy.The policy effectively improves the overall cache performance.

Key words: Non-Volatile Memory(NVM), multicore processor, cache, reuse information, bypass policy, energy consumption

中图分类号:

TP39

焦童, 陈玲玲, 安鑫, 李建华. 基于重用信息的非易失性缓存动态旁路策略[J]. 计算机工程, 2021, 47(4): 158-165.

JIAO Tong, CHEN Lingling, AN Xin, LI Jianhua. Reuse Information-based Dynamic Bypass Policy for Non-Volatile Cache[J]. Computer Engineering, 2021, 47(4): 158-165.

http://www.ecice06.com/CN/Y2021/V47/I4/158

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参考文献

[1] HE Yanxiang,SHEN Fanfan,ZHANG Jun,et al.Cache optimization approaches of emerging non-volatile memory architecture:a survey[J].Journal of Computer Research and Development,2015,52(6):1223-1241.(in Chinese)何炎祥,沈凡凡,张军,等.新型非易失性存储器架构的缓存优化方法综述[J].计算机研究与发展,2015,52(6):1223-1241.
[2] SHEN Zhirong,XUE Wei,SHU Jiwu.Research on new non-volatile storage[J].Journal of Computer Research and Development,2014,51(2):445-453.(in Chinese)沈志荣,薛巍,舒继武.新型非易失存储研究[J].计算机研究与发展,2014,51(2):445-453.
[3] MOINUDDIN K Q,MICHELE M F,ASHISH J.Preset:improving performance of phase change memories by exploiting asymmetry in write times[C]//Proceedings of ISCA'12.New York,USA:ACM Press,2012:380-391.
[4] SUN Guangyu,DONG Xiangyu,XIE Yuan,et al.A novel architecture of the 3D stacked MRAM L2 cache for CMPs[C]//Proceedings of 2009 IEEE International Symposium on High Performance Computer Architecture.Washington D.C.,USA:IEEE Press,2009:239-249.
[5] WU Xiaoxia,LI Jian,ZHANG Lixin,et al.Hybrid cache architecture with disparate memory technologies[C]//Proceedings of ISCA'09.New York,USA:ACM Press,2009:34-45.
[6] JUNWHAN A,SUNGJOO Y,KIYOUNG C.DASCA:dead write prediction assisted STT-RAM cache architecture[C]//Proceedings of 2014 IEEE International Symposium on High Performance Computer Architecture.Washington D.C.,USA:IEEE Press,2014:25-36.
[7] ZHANG Chao,SUN Guangyu,LI Peng,et al.SBAC:a statistics based cache bypassing method for asymmetric-access caches[C]//Proceedings of 2014 International Symposium on Low Power Electronics and Design.Washington D.C.,USA:IEEE Press,2014:345-350.
[8] SUN Guangyu,ZHANG Chao,LI Peng,et al.Statistical cache bypassing for non-volatile memory[J].IEEE Transac-tions on Computers,2016,65(11):3427-3440.
[9] ANTONIO G,CARLES A,MATEO V.A data cache with multiple caching strategies tuned to different types of locality[C]//Proceedings of the 9th International Conference on Supercomputing.New York,USA:ACM Press,1995:338-347.
[10] JOHNSON T L,CONNORS D A,MERTEN M C,et al.Run-time cache bypassing[J].IEEE Transactions on Computers,1999,48(12):1338-1354.
[11] WU Xiaoxiao,LI Jian,ZHANG Lixin,et al.Power and performance of read-write aware hybrid caches with non-volatile memories[C]//Proceedings of 2009 Conference on Design,Automation and Test in Europe.Washington D.C.,USA:IEEE Press,2009:737-742.
[12] WANG Z,JIMENEZ D A,XU C,et al.Adaptive placement and migration policy for an stt-ram-based hybrid cache[C]//Proceedings of 2014 IEEE International Symposium on High Performance Computer Architecture.Washington D.C.,USA:IEEE Press,2014:13-24.
[13] QUAN Baixing,ZHANG Tiefei,CHEN Tianzhou,et al.Prediction table based management policy for STT-RAM and SRAM hybrid cache[C]//Proceedings of 2012 International Conference on Computing and Convergence Technology.Washington D.C.,USA:IEEE Press,2012:1092-1097.
[14] JOHNSON T L,HWU W M W.Run-time adaptive cache hierarchy management via reference analysis[C]//Proceedings of the 24th International Symposium on Computer Architecture.New York,USA:ACM Press,1997:315-326.
[15] MAZEN K,YAN S.Counter-based cache replacement and bypassing algorithms[J].IEEE Transactions on Computers,2008,57(4):433-447.
[16] WOO S C,OHARA M,TORRIE E,et al.The SPLASH2 programs:characterization and methodological considera-tions[C]//Proceedings of 1995 International Symposium on Computer Architecture.New York,USA:ACM Press,1995:24-36.
[17] CARLSON T E,HEIRMAN W,EECKHOUT L,et al.Sniper:exploring the level of abstraction for scalable and accurate parallel multi-core simulations[C]//Proceedings of 2011 International Conference for High Performance Computing,Networking,Storage and Analysis.New York,USA:ACM Press,2011:1-12.
[18] ABELLA J,GONZÁLEZ A,VERA X,et al.IATAC:a smart predictor to turn-off L2 cache lines[J].ACM Transactions on Architecture and Code Optimization,2005,2(1):55-77.
[19] DONG Xiangyu,XU Cong,XIE Yuan,et al.Nvsim:a circuit-level performance,energy,and area model for emerging nonvolatile memory[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2012,31(7):994-1007.
[20] SUN Guangyu,ZHANG Yaojun,WANG Yu,et al.Improving energy efficiency of write-asymmetric memories by log style write[C]//Proceedings of 2012 IEEE International Symposium on Low Power Electronics and Design.Washington D.C.,USA:IEEE Press,2012:173-178.

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