摘要：

级联积分梳状(CIC)滤波器由于其结构简单、高效等优点,经常作为宽带通信芯片中的抽取器或插值器。随着通信系统以及超大规模集成电路的发展,芯片集成密度越来越高,需要对芯片中关键模块积分梳状滤波器进行面积的优化。为此,设计一种应用于无线宽带射频芯片的CIC插值滤波器。通过位宽优化方法减少滤波器内部节点位宽,并在增益校正部分采用输出截位后的正则有符号数字量编码乘法代替全位宽二进制补码乘法。实验结果表明,与优化前的CIC插值滤波器相比,该滤波器的电路面积可优化58%左右。

关键词: 级联积分梳状插值滤波器, 宽带通信芯片, 位宽优化, 增益校正, 正则有符号数字量编码乘法, 面积优化

Abstract:

Cascaded Integrator Comb(CIC)filter is always used as decimator or interpolator in broadband communication chips because of its simple construction and high efficiency.As the development of communication system and very large scale integrated circuit,chip’s integration density becomes higher,so it is important to optimize the area of CIC filter.This paper designs a CIC interpolation filter for wireless broadband radio frequency chip.The proposed design reduces the bit width of internal nodes of the filter by bit width optimization.In addition,for gain calibration,the proposed design uses Canonic Signed Digit(CSD)code multiplication cutting off the output data’s bits width,instead of two’s complement multiplication.Experimental results show that the filter optimizes the area of multipliers by 58% area reduction compared with preoptimized CIC interpolation filter.

Key words: Cascaded Integrator Comb(CIC)interpolation filter, broadband communication chip, bit width optimization;gain calibration, Canonic Signed Digit(CSD)code multiplication, area optimization

中图分类号: 

• TN47