作者投稿和查稿 主编审稿 专家审稿 编委审稿 远程编辑

计算机工程 ›› 2007, Vol. 33 ›› Issue (20): 248-250. doi: 10.3969/j.issn.1000-3428.2007.20.086

• 工程应用技术与实现 • 上一篇    下一篇

一种6读2写多端口寄存器堆的全定制实现

张 轩,李兆麟   

  1. (清华大学信息科学技术学院,CPU & SoC实验室,北京 100084)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2007-10-20 发布日期:2007-10-20

Full-custom Implementation of 6-read 2-write Multi-port Register File

ZHANG Xuan, LI Zhao-lin   

  1. (CPU & SoC Lab, Information Science and Technology College, Tsinghua University, Beijing 100084)
  • Received:1900-01-01 Revised:1900-01-01 Online:2007-10-20 Published:2007-10-20

摘要: 采用全定制设计方法实现了一种6读2写的3232位的多端口寄存器堆,包括结构设计、电路设计、版图设计、仿真验证以及建模建库。该多端口寄存器堆的读写端口互相独立,在一个时钟周期内,能够同时读出6个32位数据,并写入2个32位数据。在电路实现上,采用高速SCL结构的地址译码和分组字线的方法来减少读写延迟。采用了0.18µm 6层金属P阱CMOS工艺来实现版图设计,通过了版图验证和后端仿真。

关键词: 多端口寄存器堆, 高速SCL结构, 全定制设计, 自顶向下的设计流程

Abstract: This paper presents a full-custom design of a multi-port 32x32 bits register file with 6 read ports and 2 write ports, including architecture design, circuit design, layout design, simulation and verification, modeling and library compiling. As all read/write ports are independent, it can read 6 32-bit data and write 2 32-bit data simultaneously in one clock cycle. The design employs high-speed SCL address-decoder and word-line grouping method to reduce access delay. Its layout is realized in 0.18μm 6-layer-metal P-trap CMOS technology and passes final verification and post simulation.

Key words: multi-port register file, high-speed SCL structure, full-custom design, top-down design flow

中图分类号: