计算机工程 ›› 2012, Vol. 38 ›› Issue (22): 260-262.doi: 10.3969/j.issn.1000-3428.2012.22.065

• 开发研究与设计技术 • 上一篇    下一篇

关键循环到可重构阵列映射中的时序参数分析

朱 敏,刘雷波,尹首一,王 星,魏少军   

  1. (清华大学微电子所,北京 100084)
  • 收稿日期:2012-02-09 修回日期:2012-03-05 出版日期:2012-11-20 发布日期:2012-11-17
  • 作者简介:朱 敏(1984-),男,博士研究生,主研方向:可重构计算;刘雷波、尹首一,副教授、博士;王 星,硕士研究生;魏少军,教授、博士
  • 基金项目:

    国家“863”计划基金资助项目(2009AA011700);国家自然科学基金资助项目(60803018)

Timing Parameter Analysis of Critical Loop to Reconfigurable Array Mapping

ZHU Min, LIU Lei-bo, YIN Shou-yi, WANG Xing, WEI Shao-jun   

  1. (Institute of Microelectronics, Tsinghua University, Beijing 100084, China)
  • Received:2012-02-09 Revised:2012-03-05 Online:2012-11-20 Published:2012-11-17

摘要: 通过定义算法关键循环到可重构阵列映射的建立时间、保持时间等核心时序参数,分析存储器带宽有限、算法数据流图拓扑不规则等实际问题,给出配置时序模型的优化算法,提出路径特征等参数的描述形式,为可重构自动编译提供新的处理方式。验证结果表明,在视频算法H.264关键循环deblocking的映射过程中,该优化映射方法使得性能在原有基础上提升43%。

关键词: 关键循环, 可重构阵列, 算法映射, 时序模型, 阵列建立时间, 阵列保持时间

Abstract: Reconfigurable systems are very efficient on computing intensive domains, and critical loops of algorithms can be set up on a reconfigurable array especially. But how to mapping applications is still a hard work which limits the development of reconfigurable technique. This paper proposes a way to define timing models and method to modify the reconfigurable mapping performance. It is meaningful to the compiler designs. Memory wall on a hardware array and data flow graph topology of algorithms are considered, and the setup/hold times of a loop mapping process is also derived. The definition of path’s timing feature gives a new way to take out a reconfigurable compiler. Verification shows 43% performance improvement is achieved on mapping critical loop deblocking of H.264 decoding to a reconfigurable system.

Key words: critical loop, reconfigurable array, algorithm mapping, timing model, array setup time, array hold time

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