Application of FPGA in Radar Signal Processing

doi:10.3969/j.issn.1000-3428.2007.04.091

Computer Engineering ›› 2007, Vol. 33 ›› Issue (04): 259-262. doi: 10.3969/j.issn.1000-3428.2007.04.091

• Engineer Application Technology and Realization • Previous Articles Next Articles

Application of FPGA in Radar Signal Processing

LI Yaping1,2, ZHU NaiLi2, MENG Hongwen3, Ren Hongwei4

(1. College of Computer, Northwest Polytechnical University, Xi’an 710072; 2. College of Electronics and Information Technology, Luoyang University, Luoyang 471023; 3. The PLA of 96251 Units; 4. Luoyang Branch, Industrial and Commercial Bank of China, Luoyang 471000)

Received:1900-01-01 Revised:1900-01-01 Online:2007-02-20 Published:2007-02-20

FPGA在雷达信号处理中的应用

李雅萍1,2，朱乃立2，孟红文3，任宏伟4

(1. 西北工业大学计算机学院，西安 710072；2. 洛阳大学电子信息工程学院，洛阳 471023； 3. 中国人民解放军96251部队； 4. 中国工商银行洛阳分行，洛阳 471000)

Abstract

Abstract: By development of the digital signal processing theory and improvement of microelectronic technology, using the feature of high speed of FPGA has been the focus of research and exploitation in satisfying real time of digital signals processing in RADAR. Combining scientific research, the paper introduces architecture description of EP1S30 and IDT72V3670 chip, involves configure method. According to the need of project, it discusses the designing and debugging of electrocircuit.

Key words: Radar, Clutter rejection, FPGA

摘要： 随着数字信号处理理论和微电子技术的发展，利用FPGA的高速特性来满足雷达信号处理的实时要求，目前已经成为该领域的研究及开发热点。该文结合科研实践，介绍了EP1S30芯片和IDT72V3670芯片的技术特性与功能原理。FPGA在实际电路中的相应配置方法，围绕工程项目完成了雷达杂波抑制电路的设计与调试。

关键词: 雷达, 杂波抑制, 现场可编程门阵列

LI Yaping; ZHU NaiLi; MENG Hongwen; Ren Hongwei. Application of FPGA in Radar Signal Processing[J]. Computer Engineering, 2007, 33(04): 259-262.

李雅萍;朱乃立;孟红文;任宏伟. FPGA在雷达信号处理中的应用[J]. 计算机工程, 2007, 33(04): 259-262.

/ / Recommend / Download Citations

URL: http://www.ecice06.com/EN/10.3969/j.issn.1000-3428.2007.04.091

http://www.ecice06.com/EN/Y2007/V33/I04/259

[1]	HUANG Zhengwei, LIU Hongwei, XU Yuan. Design of Ultra-Low-Power RISC-V Dedicated Processor for IToF Sensor [J]. Computer Engineering, 2022, 48(9): 146-154.
[2]	FENG Yifei, DING Nan, YE Junchao, CHAI Zhilei. Design and Implementation of Domain-Specific Low-Latency and High-Bandwidth TCP/IP Offload Engine [J]. Computer Engineering, 2022, 48(9): 162-170.
[3]	XI Zhiwen, CAI Jingjing, YANG Wenmin, CHAI Zhilei. Concurrent Request Scheduling Mechanism for FPGA Cloud Platform Based on Microservice Architecture [J]. Computer Engineering, 2022, 48(7): 206-213.
[4]	GONG Jie, ZHAO Shuo, HE Hu, DENG Ning. Design of Quantized CNN Acceleration System Based on FPGA [J]. Computer Engineering, 2022, 48(3): 170-174,196.
[5]	HUANG Rui, JIN Guanghao, LI Lei, JIANG Wenchao, SONG Qingzeng. Design and Implementation of Accelerator for Lightweight Neural Network [J]. Computer Engineering, 2021, 47(9): 185-190,196.
[6]	ZHAO Chenyuan, LI Wenxin, ZHANG Qingxi. An Improved Real-Time Semi-Global Stereo Matching Algorithm and Its Hardware Implementation [J]. Computer Engineering, 2021, 47(9): 162-170.
[7]	DI Xinkai, YANG Haigang. FPGA-based Accelerator for Sparse Convolutional Neutral Network [J]. Computer Engineering, 2021, 47(7): 189-195,204.
[8]	LIU Pengfei, DU Xinjun. Modulation Hopping Communication Based on Three-Dimensional Chaotic System with Weighted Feedback [J]. Computer Engineering, 2021, 47(3): 183-189,195.
[9]	YUAN Jiawei, SONG Qingzeng, WANG Xuechun, JIANG Wenchao, JIN Guanghao. Performance and Power Consumption Measurement and Analysis of Edge Computing Devices [J]. Computer Engineering, 2021, 47(2): 233-238,245.
[10]	SHI Yongquan, JING Naifeng. Evaluation Method Based on FPGA Emulation for Resistive Neural Network Accelerators [J]. Computer Engineering, 2021, 47(12): 209-214.
[11]	WU Jianfeng, ZHENG Bowen, NIE Yi, CHAI Zhilei. FPGA Accelerator for 3DES Algorithm Based on OpenCL [J]. Computer Engineering, 2021, 47(12): 147-155,162.
[12]	ZHANG Hao, WEI Jinghe. Design and Verification of Efficient PLB2AXI Bus Bridge [J]. Computer Engineering, 2020, 46(8): 228-234.
[13]	SONG An, WANG Qin, GU Dawu, GUO Zheng, LIU Junrong, ZHANG Chi. FPGA-based Collection Method for Power Information of Clock Synchronization [J]. Computer Engineering, 2020, 46(6): 115-121.
[14]	LI Tao, HAN Peng, HOU Guandong, ZHAN Jiayuan. Design and Implementation of ORUDP Protocol Stack Based on FPGA [J]. Computer Engineering, 2020, 46(6): 155-163.
[15]	KONG Feiyue, JIANG Xueqin, WAN Xuefen, CHEN Sijing, CUI Jian, YANG Yi. Parallel Implementation of GPU-Based LDPC Enhanced Quasi-Maximum Likelihood Decoder [J]. Computer Engineering, 2020, 46(5): 207-215.

Please choose a citation manager

Content to export

Application of FPGA in Radar Signal Processing

FPGA在雷达信号处理中的应用

PDF

Knowledge

Cited

Abstract

Cite this article

share this article

References

Related Articles 15

Recommended Articles

Metrics

Comments

模态框（Modal）标题

Please choose a citation manager

Content to export

Application of FPGA in Radar Signal Processing

FPGA在雷达信号处理中的应用

PDF

Knowledge

Cited

Abstract

Cite this article

share this article

References

Related Articles 15

Recommended Articles

Metrics

Comments