Abstract: In the embedded environment, demand of memory system is gradually increasing. More and more embedded systems adopt a high speed memory system to support the systems’ running and store a large number of data. As the speed and the volume of a memory system are extending, how to design a high speed memory system has become a problem which should be researched on. This paper uses a large amount of the DDR memory system design as an example to focus on the signal integrity problem. Using signal integrity simulation method, this paper analyzes and discusses how the proper signal termination modes and signal routing rules affect signal integrity. The method can be efficiently used in many different volumes of high speed memory system design, also in the latest DDR2 memory system design. With the method, implementation of the memory system gains a good result.

Key words: Signal integrity simulation, system on a programmable chip(SoPC), Memory system, DDR

摘要： 嵌入式环境中存储需求在不断地增长，越来越多的嵌入式系统采用高速存储单元支持系统运行以及大规模的数据存储。随着嵌入式存储系统的速度和容量的扩展，如何设计高速的存储系统成为需要研究的问题。该文从信号完整性的角度，以一种海量DDR存储系统设计为实例，利用信号完整性仿真方法，分析和探讨了适当的信号线终结方式和布线规则对信号完整性的影响。该方法适用于不同容量的高速存储系统设计和高速DDR2存储系统，实际应用表明了该方法具有良好的效果。

关键词: 信号完整性仿真, 片上可编程系统, 存储系统, DDR

CLC Number: 

• TP273