Abstract: As FPGA is reconfigurable in logic and can be readback in data, this paper designs a reconfigurable system based on Xilinx VirtexTM FPGA. CPU and CPLD are used to configure FPGA which selects a SelectMAP configuration mode and readback configuration data in it. The paper introduces the process of the system to implement the configuration and readback function. Part of the results are shown in wave charts.

Key words: Reconfigurable, FPGA, SelectMAP, CPLD, Readback, Virtex

摘要： Xilinx Virtex系列FPGA具有配置逻辑可重构、配置数据可回读的特点，该文设计了基于Virtex FPGA的一种可重构系统。FPGA采用SelectMAP配置方式，在CPU和CPLD控制下实现了配置数据加载和回读的功能。给出了系统配置FPGA和回读其配置数据的流程及相应的波形图。
关键词：

关键词: 可重构, FPGA, SelectMAP, CPLD, 回读, Virtex

CLC Number: 

• TP303