Abstract: High-level design technology in VLSI is a main trend in EDA, while high level synthesis is the key in it. Scheduling and interconnection is an important task at high level synthesis. This paper introduces some algorithms and provides a new idea of application of DVS technology which can dynamically change clock speed and supply voltages under satisfying performance and time constraints in order to reduce power consumption. It still makes, a feasible research plan.

Key words: VLSI, high level synthesis, schedule, DVS, interconnection

摘要： VLSI高层次设计技术是近年来系统设计自动化研究的主要方向，高层次综合设计是高层次设计技术的关键，其主要任务是调度和互连。该文介绍了若干基本的调度和互连算法，提出将DVS技术应用于高层次综合设计中，实现在满足任务行为的约束条件下，动态改变时钟的速度和电源电压达到降低功耗的目的，制定了可行的研究实施方案。

关键词: VLSI, 高层综合设计, 调度, DVS, 互连

CLC Number: 

• N945