Abstract:
Secure hash algorithms are important tools for cryptographic application such as digital signatures. To satisfy the requirements of computation speed, the paper divides SHA-1 into five modules of hardware architecture. Every module works independently and every module is optimized. It do not affect other modules when one module is modified.
Key words:
hash algorithm,
SHA-1 algorithm,
FPGA,
VHDL
摘要: SHA-1算法是目前常用的安全散列算法,被广泛地应用于电子商务等信息安全领域。为了满足安全散列算法的计算速度,该文将SHA-1分成5个硬件结构模块来实现,每个模块可以独立工作。对其进行了优化,达到了缩短关键路径的目的,提高了计算速度。独立的模块使得对每个模块的修改都不会影响其他模块的工作,为模块的进一步优化提供了方便。
关键词:
散列算法,
SHA-1算法,
现场可编程门阵列,
硬件描述语言
CLC Number:
SUN Li; MU Dejun; LIU Hang. Design and Implementation of SHA-1 Algorithm Based on FPGA[J]. Computer Engineering, 2007, 33(14): 270-271,.
孙 黎;慕德俊;刘 航. 基于FPGA的SHA-1算法的设计与实现[J]. 计算机工程, 2007, 33(14): 270-271,.