Abstract: This paper introduces the design and implementation of an AHB bus bridge of crossing clock domains. By adopting the state machine design method and using the merging of prevent-deadlock and break-deadlock to deal with deadlock, the bridge can support read/write burst, pre-fetch operation for reading, deprived bus arbiter etc operations and simplify the implementation. Performance test indicates that it can improve the system bandwidth and timing performance greatly.

Key words: AHB bus, bridge, crossing clock domains

摘要： 介绍一种跨时钟域的32位AHB总线桥的设计与实现。通过采用状态机设计以及使用预防死锁与解除死锁相结合的方法解决死锁，使得该桥支持读写burst、读预取、总线抢占式仲裁等多种操作并且简化了设计。性能测试表明，该桥能极大提高复杂SoC系统的系统带宽和时序性能。

关键词: AHB总线, 桥, 跨时钟域

CLC Number: 

• TP391