Abstract: According to the features of Universal Asynchronous Receiver Transmitter(UART), a FPGA-based embedded design algorithm is proposed. The algorithm includes state machine design and level design techniques. The transmission function of full-duplex to receive/sends data is realized. The functional test circuit of UART is also designed. Experimental results show that the design has the advantages of programmable digit of the send/receive data and functional expansion etc.

Key words: universal asynchronous receiver transmitter, FPGA, finite state machine

摘要： 针对通用异步收发器(UART)的特点，提出一种基于FPGA芯片的嵌入式设计算法，其中包括状态机设计技术和层次设计方法，实现了数据传输的全双工收/发功能，设计了UART的功能测试电路。结果表明，该设计具有可编程收/发数据位数和提供功能扩展等优点。

关键词: 通用异步收发器, 现场可编程门阵列, 有限状态机

CLC Number: 

• TP18