Abstract: Aiming at the problem existed in traditional PCI bus, a scheme of serial RapidIO-PCI bridge in mode of asynchronous FIFO memory is proposed. The structure and its performance of high speed bus for RapidIO are introduced. According to the protocol of PCI and RapidIO, the key section of this bridge is designed, which is inspected and implemented. Experimental results show this scheme is effective.

Key words: high speed bus, RapidIO interconnected technology, bridge, FPGA platform

摘要： 针对传统总线PCI存在的问题，提出异步FIFO存储转发模式的串行RapidIO-PCI转接桥方案，介绍RapidIO高速总线的体系结构及其性能优势，根据PCI和RapidIO协议，给出转接桥关键部分结构的设计，并在FPGA上的进行验证与实现。实验结果表明，该方案是有效的。

关键词: 高速总线, RapidIO互联技术, 转接桥, FPGA平台

CLC Number: 

• TP334.4