Abstract: As the progress of storage access speed is much slower than the communication transport rate, the storage bandwidth becomes the bottleneck of the router’s performance. This paper proposes a high efficient parallel storage access mechanism implemented by a simply approach combining hardware and software. Two same size output buffers are designed for alleviating the bottleneck caused by single storage interface. A paired access structure is designed by software to take use of the two same size output buffers parallely. The test results indicate that this mechanism effectively increases the router’s throughput and storage access speed.

Key words: storage bandwidth, parallel storage mechanism, router

摘要： 访存速率远滞后于传输速率的发展，成为影响路由器性能的最大瓶颈。该文提出一种高效并行存储设计方案，通过简洁的软硬件协同技术实现，硬件实现2个同样大小的输出端缓冲区，消除由于单个存储接口可能引起的系统瓶颈，软件设计为成对存储信元的结构。试验结果表明，该机制有效提高了存储访问速度和路由器的吞吐率。

关键词: 存储带宽, 并行存储机制, 路由器

CLC Number: 

• TP273