Abstract: Memory Management Unit(MMU) which is based on MIPS32 4kc processor is designed. The module checks the address from the processor core, and translates it to physical address statically or dynamically. TLB is the core of dynamical mapping and is implemented by using three stage pipelines. Moreover, ITLB and DTLB which are shadows of JTLB are designed to accelerate address translation. The module and processor are verified on FPGA board running Linux and the hardware cost is about 32K logical gates.

Key words: Memory Management Unit(MMU), Translation Look-aside Buffer(TLB), MIPS processor

摘要： 设计MIPS32 4kc处理器内存管理单元(MMU)，该模块对处理器地址进行合法性检查，并按照不同的地址空间对虚拟地址进行静态或动态映射。在硬件上采用三级流水线方式实现JTLB，并为处理器指令端口和数据端口设计相应的快表以提高TLB的查询速度。MMU与总线接口模块的时序采用简化的AMBA协议，与处理器进行联合调试并运行Linux操作系统，同时在功能上通过FPGA验证。该模块经过DC综合后，面积约为32K等效逻辑门。

关键词: 内存管理单元, 地址转换后备表, MIPS处理器

CLC Number: 

• TP311.52