Abstract:
This paper provides two methods of Dynamic Partial Reconfiguration(DPR) based on EAPR flow and introduces the process of DPR through time/space share. By using the embedded CPU(Power PC405) on the board to control the other programmable logic resoures, a dynamic selfreconfigure is designed successfully. Both two methods are verified on the VirtexII Pro development system, which indicates that the DPR method can implement a much larger design using much smaller FPGA resources.
Key words:
EAPR flow,
FPGA,
Dynamic Partial Reconfiguration(DPR),
time/space share
摘要: 介绍实现动态局部可重构的方法,以EAPR流程为例,阐述通过时/空复用技术实现动态局部自动重构的基本过程。在此基础上,使用芯片内嵌的硬核处理器Power PC405来调度和管理芯片上其他可编程逻辑资源的自重构过程。在VirtexII Pro开发板上进行验证,结果表明,使用较小容量的FPGA硬件资源,可完成超过其容量规模的系统设计。
关键词:
EAPR流程,
现场可编程门阵列,
动态局部可重构,
时/空复用
CLC Number:
XUE Jian-Wei, ZHANG Jie, GUAN Yong. Implementation of Dynamic Partial Reconfiguration Based on EAPR Flow[J]. Computer Engineering, 2010, 36(23): 252-254.
薛建伟, 张杰, 关永. 基于EAPR流程的动态局部可重构实现[J]. 计算机工程, 2010, 36(23): 252-254.