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计算机工程

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考虑缺陷率模型的多项目晶圆布图规划算法

张腾,史峥,廖海涛   

  1. (浙江大学电气工程学院超大规模集成电路设计研究所,杭州 310027)
  • 收稿日期:2013-02-20 出版日期:2014-04-15 发布日期:2014-04-14
  • 作者简介:张 腾(1988-),男,硕士研究生,主研方向:集成电路计算机辅助设计;史 峥,副研究员;廖海涛,硕士研究生。
  • 基金资助:
    国家自然科学基金资助项目(61204111)。

Multi-project Wafer Floorplanning Algorithm Considering Defect Rate Model

ZHANG Teng, SHI Zheng, LIAO Hai-tao   

  1. (Institute of VLSI, College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China)
  • Received:2013-02-20 Online:2014-04-15 Published:2014-04-14

摘要: 针对随机缺陷会降低多项目晶圆实际产出的问题,提出一种新的多项目晶圆布图规划算法。通过在布图规划中引入缺陷率模型的方法,增加芯片产量的裕量,降低因随机缺陷造成的产量损失。同时优化模拟退火流程,使得在布图尺寸约束条件下,布图规划过程能够跳出局部最优解陷阱。对工业实例进行布图规划的结果表明,该算法能够接受不满足布图尺寸约束条件的中间结果,从而遍历解空间,得到全局最优的布图,并且相对已有算法,使用相同数量晶圆进行切割时,算法的布图结果增加了137%的芯片产量的总裕量,同时,降低了25%的工作芯片所需要生产的晶圆数量。

关键词: 多项目晶圆, 布图规划, 模拟退火算法, 代价函数, 缺陷率模型, 布图尺寸约束

Abstract: To address yield loss from random defects, a new Multi-project Wafer(MPW) floorplanning algorithm is proposed. This proposed algorithm can increase production margin as well as reduce fabrication loss caused by random defects by introducing defect models, and simulated annealing process is modified to escape locally optimal solution traps under Reticle Size Constraint(RSC). By carrying out industrial cases, the proposed algorithm can search solution space and find global optimal solution by accepting interim floorplanning results, and floorplanning result illustrates proposed algorithm increases total chip production margin by 137%, and reduces required wafer number to obtain enough volume of chip for each integrated circuit design by 25%, compared with existing algorithms.

Key words: Multi-project Wafer(MPW), floorplanning, simulated annealing algorithm, cost function, defect rate model, Reticle Size Constraint(RSC)

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