摘要： 本文提出一种在VLSI LSSD可测试性设计中采用特殊的三值时钟信号取代二值时钟信号的新方案。一方面电路保持了LSSD方法提高电路可测试性的优点。另一方面由于采用了三位逻辑技术,原来LSSD方法中所需要的一根模式选择信号线可以省去。鉴于在原LSSD方法中这根信号线需要连接至电路中的每一个触发器,因此它的省去对降低VLSI电路的连接复杂性及节省基片面积是极有意义的。文中详述了新方案的工作原理并给出了用CMOS电路实现该方案的电路设计,并将三值方案与传统的二值方案及带译码器的二值方案进行了比较。

Abstract: A new scheme is proposed which uses ternary clocking signals to replace binary clocking signals in VLSI LSSD testability designs. This scheme has the same advantage of high testability as the binary LSSD method, but it eliminates the mode selecting signal line required by the binary LSSD method to route this line to each flip-flop. The saving is significant in regard to the circuit connection and chip area. This paper describes the new ternary scheme in detail, and also suggests appropriate circuit designs using CMOS technology. Furthermore, comparisons are made between ternary LSSD and binary LSSD and between that and a scan scheme using binary with a local decoder.