摘要： 本文提出一种以宿主机+协处理机构造的顺序推理机结构,协处理机采用 INMOS公司的RISC芯片Transputer并以流水线方式工作。文中较为详细地讨论了协处理机中处理器之间的通讯、同步以及系统回溯的实现。
Abstract: A sequential inference machine architecture consisting of a host and a coprocessor is presented. The coprocessor uses the INMOS RISC chip-transputer and operates in pipeline.
Communications and synchronization between processors in the coprocessor and implementation of system backtracking are discussed in detail.
吴荣泉,汤慧媛,李永坚. 顺序推理机ECI-SIM[J]. , 1991, 17(02): 9-13.
Wu Rongquan. ECI-SIM: A SEQUENTIAL INFERENCE MACHINE[J]. , 1991, 17(02): 9-13.