摘要： 银河TS-1微处理器是国防科技大学计算机学院自行设计的具有自主版权的32位嵌入式微处理器。参考标准DLX5级流水线设计了银河TS-1流水线核基本的指令处理通路和数据通路，并以此为基础提出了一种更为高效的6级流水线：取指，译码，操作数准备，ALU执行，数据获取，写回。此6级流水线与5级流水线相比，硬件开销增加很少，但加速比大于1.54。

关键词: RISC流水线核, 流水线设计, 指令处理通路, 数据通路, 嵌入式微处理器

Abstract: YH TS-1 is a 32-bit embedded microprocessor designed by School of Computer, National University of Defense Technology. By referring to the standard DLX five-stage pipeline, the basic instruction processing path and datapath of YH TS-1 are designed. And beyond this, a six-stage pipeline: Instruction fetch, instruction decode, operand prepare, ALU, data access, write back are developed. In comparison with the five-stage pipeline, with a little hardware cost, a speedup about 1.54 is gained.

中图分类号: 

• TP332