摘要： 在传统的软硬件协同设计中，硬件采用的是RTL描述(用硬件设计语言HDL描述)，而软件通常采用C或者C++语言进行描述，这种语言描述的不一致会加大协同验证仿真的难度，从而导致系统设计过程的反复。文章提出了一种基于WISHBONE总线协议标准的用SystemC语言描述的虚部件库设计与管理方法，可以降低SoC系统设计的复杂度，从而加快SoC系统设计的过程。

关键词: SoC, SystemC, WISHBONE总线, 虚部件库

Abstract: As usually using HDL to descript hardware in RTL level and using C or C++ programming language to descript software, it brings the difficulty of coverification and cosimulation so as to lead the repeating of design process in traditional HW/SW codesign. Based on WISHBONE protocol standard, this paper proposes a method of designing and managing virtual component library described with SystemC, it can reduce the complexity of SoC system so as to quicken the design process.

中图分类号: 

• TN402