摘要： 二进制翻译一般是为了解决遗产代码的问题,同时也可以实现不同硬件平台之间软件的通用。解释执行是二进制翻译不可或缺的一部分。CISC结构的x86指令由于可变长,反汇编较固定指令字长的RISC结构复杂。为了后续的模拟,需要把x86的机器码提升为和汇编码平行的一种结构——IR1结构。该文讨论了这种IR1存放的缓冲区的管理策略对系统性能的影响。
关键词:
二进制翻译,
反汇编,
动态优化,
程序块
Abstract: Binary translation is applied for the legacy code. Binary code can be executed in different hardware platforms. Interpreting is necessary to the binary translation. Length of the instruction of x86 is variable, which make more difficult to disassemble than the structure of RISC. For the next step of emulating, the binary code of x86 should be converted to the structure, IR1 structure. This paper studies the management of the IR1 buffer effecting on the system performance.
中图分类号:
唐锋,武成岗,张兆庆,冯晓兵,马湘宁. 二进制翻译中解释器指令缓冲区管理策略分析[J]. , 2005, 31(11): 80-82.
TANG Feng, WU Chenggang, ZHANG Zhaoqing, FENG Xiaobing, MA Xiangning. Performance Analysis of Instruction Buffer Management in the Interpreter in Binary Translation[J]. , 2005, 31(11): 80-82.