摘要： 基于提升的小波变换算法,提出了一种新的功率面积有效的5-3和9-7小波变换的VLSI实现结构。采用时分复用和嵌入式并行流水线技术优化设计结构,有效地减少了所用乘法器、加法器运算单元和寄存器单元数量,以及对存储器的访问次数,从而有效地减少系统占用面积和功耗。系统实现了每一个时钟产生一个输出,输入信号的细节分量和近似分量交替输出。该结构具有简单、规则,以及扩展性好的特点,非常适合于VLSI设计实现。

关键词: 提升小波变换, 时分复用技术, 嵌入式流水线技术, VLSI

Abstract: A Novel area and power efficient VLSI architecture for 5-3 and 9-7 wavelet transform, based on the lifting schemes, is proposed.Where, the time division multiplexing and embedded pipeline techniques are adopted to optimize the design of the architectures. It reducessignificantly the numbers of the multipliers, adders and registers required, and the amount of memory access, leading to decrease efficiently theoccupied area and power consumption of the design. The system is designed to generate one output in every clock cycle, the detail component andthe approximation of the input signal are available alternately. The presented architecture is simple, regular , scalable, and suited for VLSIimplementation.

中图分类号: 

• TN702