摘要： 定义了时钟单位阶跃信号C(n),提出了一种利用带相对时钟坐标的逻辑方程表示逻辑信号的方法;通过对所设计的DDR SDRAM控制器的读写时序的分析,建立了控制器主要信号的时序表达式,并利用所建立的时钟逻辑方程对DDR控制器的读过程进行了简单的分析。这种方法可以应用到内存系统的带宽和延时估计方面,比较直观。

关键词: 时钟逻辑方程, DDRSDRAM控制器, 时序模型

Abstract: The paper defines the clock unit stepping function and proposes a kind of timing logical expression for DDR SDRAM controller signals, establishing the timing sequential expression of the major signals through the analysis of the burst read/write operation of the DDR SDRAM controller. And its also gives an example of application using this kind of timing expression. This method can be used to estimate the static timing delay value and bandwidth of the main memory channel.

中图分类号: 

• TP333