摘要： 随着集成电路的飞速发展,芯片能否进行全面成功的静态时序分析已成为其保证是否能正常工作的关键。该文结合一款面向个人信息处理终端的SoC芯片探讨了静态时序分析(STA)流程中时钟约束的关键技术问题,对未来基于静态时序分析进行SoC芯片的优化设计有重要的参考价值。

关键词: SoC设计, 时钟问题, 静态时序分析

Abstract: With the fast development of the integrated circuit,the key to working silicon usually lies in successful completion of static timing analysis performed on a particular design.The paper presents the key technology of the clock constraints in the STA flow on a SoC chip for PDA.In summary,the knowledge will have an important effect on the future SoC design and optimization based on STA.

中图分类号: 

• TN403