摘要： 描述了一款适用于超长指令字数字信号处理器的64位加法器的设计。该加法器高度可重构，可以支持2个64位数据的加法运算、4个32位数据的加法运算、8个16位数据的加法运算以及16个8位数据的加法运算。它结合了Brent-Kung对数超前进位加法器和进位选择加法器的优点，使得加法器的面积和连线减少了50%，而延时与加法器的长度的对数成正比。仿真结果表明，在典型工作条件下，采用0.18μm工艺库标准单元，其关键路径的延时为0.83ns，面积为0.149mm2，功耗仅为0.315mW。
关键词:
可重构加法器,
Brent-Kung树,
进位选择,
功耗延时积
Abstract: This paper presents the design of a highly re-configurable 64-bit adder, which is well suitable for VLIW digital signal processor. The adder can add two 64-bit operands, four 32-bit operands, eight 16-bit operands, or sixteen 8-bit operands. It is the hybrid of binary carry look-ahead adder of Brent-Kung, and the carry select adder. By using this approach, the area and wiring of the adder is reduced by 50%, keeping the delay proportional to Olog n. Simulation results indicate that, typical conditions in standard cell using 0.18μm technology, the proposed adder can complete 64-bit addition in 0.83 ns and dissipates only 0.315mW with the area of 0.149mm2.
Key words:
re-configurable adder,
Brent-Kung tree,
carry select,
power- delay product
中图分类号:
张志伟;马 鸿;李立健;王东琳. VLIW数字信号处理器64位可重构加法器的设计[J]. 计算机工程, 2007, 33(16): 29-31，3.
ZHANG Zhi-wei; MA Hong; LI Li-jian; WANG Dong-lin. Design of VLIW Digital Signal Processor’s 64-bit Configurable Adder[J]. Computer Engineering, 2007, 33(16): 29-31，3.