计算机工程 ›› 2009, Vol. 35 ›› Issue (12): 1-4.doi: 10.3969/j.issn.1000-3428.2009.12.001

• 博士论文 •    下一篇

数字信号处理器中高性能可重构加法器设计

马 鸿,李振伟,彭思龙   

  1. (中国科学院自动化研究所国家专用集成电路设计工程研究中心,北京 100080)

  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2009-06-20 发布日期:2009-06-20

High Performance Re-configurable Adder Design for Digital Signal Processor

MA Hong, LI Zhen-wei, PENG Si-long   

  1. (National ASIC Design Engineering Research Center, Institute of Automation, Chinese Academy of Sciences, Beijing 100080)

  • Received:1900-01-01 Revised:1900-01-01 Online:2009-06-20 Published:2009-06-20

摘要: 设计一款适用于高性能数字信号处理器的16位加法器。该加法器结合条件进位选择和条件“和”选择加法器的特点,支持可重构,可以进行2个16位数据或者4个8位数据的加法运算,同时对其进位链进行优化。相对于传统的条件进位选择加法器,在典型工作条件下,采用0.18 m工艺库标准单元,其延时降低46%,功耗降低5%。

关键词: 条件进位选择加法器, 条件“和”选择加法器, 可重构加法器

Abstract: This paper presents the design of a high performance re-configurable 16-bit adder, which is well suitable for digital signal processor. The adder can add two 16-bit operands or four 8-bit operands. It is a hybrid of Conditional Carry Select adder(CCS) and Conditional Sum Select adder(CSS) with which the carry chain is also optimized. Simulation results show that the delay is reduced by 46% and the power is 5% lower compared with the general CCS under typical conditions with standard cell using 0.18 m technology.

Key words: Conditional Carry Select adder(CCS), Conditional Sum Select adder(CSS), re-configurable adder

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