摘要： 介绍一款网络处理器的设计方案，根据该网络处理器体系结构的特点，论述针对数据处理内核的原型验证技术。讨论原型验证平台的结构，在采用多片FPGA进行原型验证时要考虑复位时序、时钟同步等因素，以及原型验证过程。实验结果表明，该原型验证平台有效验证了网络处理器核心部件的设计功能。

关键词: 网络处理器, 数据处理内核, 原型验证

Abstract: This paper introduces the scheme of a network processor. The prototype of the data processing core which is the core block of network processor verification method is described. The architecture of the prototype verification platform, the reset timing and clock synchronized for prototype verification with multi-FPGAs and the procedure of verification are discussed. Experimental result on this platform verifies the feasibility of this prototype verification method.

Key words: network processor, data processing core, prototype verification

中图分类号: 

• TP393