计算机工程 ›› 2010, Vol. 36 ›› Issue (3): 243-245.doi: 10.3969/j.issn.1000-3428.2010.03.082

• 工程应用技术与实现 • 上一篇    下一篇

网络处理器数据处理内核的设计与实现

李 苗,王叶辉,周彩宝   

  1. (华东计算技术研究所,上海 200233)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2010-02-05 发布日期:2010-02-05

Design and Realization of Data Processing Core in Network Processor

(East China Institute of Computer Technology, Shanghai 200233)   

  1. (East China Institute of Computer Technology, Shanghai 200233)
  • Received:1900-01-01 Revised:1900-01-01 Online:2010-02-05 Published:2010-02-05

摘要: 通用处理器和专用芯片ASIC的数据处理能力无法满足日益增长的网络带宽和各种复杂网络协议的要求,针对该问题,研究网络处理器的系统结构,讨论网络处理器中数据处理内核的设计实现,提出一种可编程的精简指令集计算机(RISC)处理器微结构,对其进行现场可编程门阵列(FPGA)原型验证,结果证明了该设计方案的有效性。

关键词: 网络处理器, 数据处理内核, 流水线

Abstract: Data processing capability of General Purpose Processor(GPP) and Application Specific Integrated Circuit(ASIC) can not meet the requirements of increasing network bandwidth and complex protocols, so that this paper researches the architecture of Network Processor(NP), discusses the design and realization of data processor core in network processor, and proposes a programmable Reduced Instruction Set Computer(RISC) micro-architecture of processor. It demonstrates the feasibility of design scheme through Field Programmable Gate Array(FPGA) prototype.

Key words: Network Processor(NP), data processing core, pipeline

中图分类号: