摘要：

针对嵌入式领域低开销、高性能的应用需求, 设计一种基于RISC-V开源指令集架构的32 bit微处理器。采用顺序发射、顺序执行、乱序写回的五级流水线结构, 实现了整型和乘除法指令集模块组合。为了应对流水线冲突, 处理器采用动态分支预测技术, 设计数据相关性控制和乱序写回机制。使用Verilog进行设计并采用先进高性能总线(AHB)和高级外围总线(APB)为互联总线协议构建片上系统(SoC)。在仿真环境下通过编写RV32IM汇编指令测试程序, 完成对处理器逻辑功能的验证。在Vivado综合工具下添加时序约束和物理约束条件后, 对处理器代码进行逻辑综合并分析处理器硬件资源利用情况, 最后将综合生成的码流文件下载到Xilinx Artix-7 (XC7A200T-2FBG484I) 现场可编程门阵列(FPGA)开发板中并以50 MHz的主频运行CoreMark程序, CoreMark跑分达到3.25 CoreMark/MHz。实验结果表明, 处理器性能跑分与ARM Cortex-M3系列处理器基本持平, 在各项技术对比指标相同的前提下, 所设计的处理器跑分均优于RISC-V处理器对比项。所设计的处理器逻辑功能正确, 使用较低的硬件开销, 取得相对较高的性能指标, 适用于成本受限的高性能嵌入式应用领域。

关键词: 嵌入式, RISC-V架构, 五级流水线, 分支预测, 乱序写回, 先进高性能总线

Abstract:

To meet the requirements of low-overhead and high-performance applications in the embedded field, a 32 bit microprocessor based on the RISC-V open-source instruction set architecture has been developed. The processor adopts a five-stage pipeline structure of sequential launch, sequential execution, and out-of-order write back and realizes a combination of integer and multiply-divide instruction set modules. To cope with pipeline conflicts, the processor adopts a dynamic branch-prediction technique and designs data-correlation control and write back disorder mechanisms. The processor is designed using Verilog and builds a System on Chip (SoC) using an Advanced High-performance Bus (AHB) and an Advanced Peripheral Bus (APB) as interconnecting bus protocols. The processor logic functions are verified by writing RV32IM assembly instruction test programs in a simulation environment. Add timing constraints and physical constraints under the Vivado synthesis tool to perform logical synthesis on the processor code and analyze the utilization of processor hardware resources, and the synthesized code stream file is downloaded to the Xilinx Artix-7 (XC7A200T-2FBG484I) Field Programmable Gate Array(FPGA) development board and runs at a main frequency of 50 MHz. In the CoreMark program at 50 MHz, the CoreMark running points reaches 3.25 CoreMark/MHz. The validation results show that the processor performance running points is the same as that of the ARM Cortex-M3 series processors, and under the premise of the same technical comparison indexes, the processor running points is better than that of the RISC-V processor comparison item. The designed processor logic function is correct and uses a low hardware overhead to achieve relatively high-performance indicators suitable for cost-constrained high-performance embedded applications.

Key words: embedded, RISC-V architecture, five-stage pipeline, branch prediction, out-of-order write back, Advanced High-performance Bus (AHB)