[1] YANG Tongxin,UKEZONO T,SATO T.A low-power high-speed accuracy-controllable approximate multiplier design[C]//Proceedings of the 23rd Asia and South Pacific Design Automation Conference.Washington D.C.,USA:IEEE Press,2018:605-610. [2] HA Minho,LEE S.Multipliers with approximate 4-2 compressors and error recovery modules[J].IEEE Embedded Systems Letters,2017,10(1):6-9. [3] KULKARNI P,GUPTA P,ERCEGOVAC M.Trading accuracy for power with an underdesigned multiplier architecture[C]//Proceedings of the 24th Internatioal Conference on VLSI Design.Washington D.C.,USA:IEEE Press,2011:346-351. [4] SHAFIQUE M,HAFIZ R,REHMAN S,et al.Cross-layer approximate computing:from logic to architectures[C]//Proceedings of the 53rd Annual Design Automation Conference.New York,USA:ACM Press,2016:99. [5] BHARDWAJ K,MANE P S,HENKEL J.Power-and area-efficient approximate wallace tree multiplier for error-resilient systems[C]//Proceedings of the 15th International Symposium on Quality Electronic Design.Washington D.C.,USA:IEEE Press,2014:263-269. [6] VENKATACHALAM S,KO S B.Design of power and area efficient approximate multipliers[J].IEEE Transactions on Very Large Scale Integration Systems,2017,25(5):1782-1786. [7] ZERVAKIS G,TSOUMANIS K,XYDIS S,et al.Design-efficient approximate multiplication circuits through partial product perforation[J].IEEE Transactions on Very Large Scale Integration Systems,2016,24(10):3105-3117. [8] QIQIEH I,SHAFIK R,TARAWNEH G,et al.Energy-efficient approximate multiplier design using bit significance-driven logic compression[C]//Proceedings of the Conference on Design,Automation and Test in Europe.New York,USA:ACM Press,2017:7-12. [9] LIU Cong,HAN Jie,LOMBARDI F.A low-power,high-performance approximate multiplier with configurable partial error recovery[C]//Proceedings of 2014 Design,Automation and Test in Europe Conference and Exhibition.Washington D.C.,USA:IEEE Press,2014:1-4. [10] KIM M S,DEL BARRIO A A,HERMIDA R,et al.Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks[C]//Proceedings of the 23rd Asia and South Pacific Design Automation Conference.Washington D.C.,USA:IEEE Press,2018:617-622. [11] KAHNG A B,KANG S.Accuracy-configurable adder for approximate arithmetic designs[C]//Proceedings of the 49th Annual Design Automation Conference.New York,USA:ACM Press,2012:820-825. [12] GUPTA V,MOHAPATRA D,PARK S P,et al.IMPACT:imprecise adders for low-power approximate computing[C]//Proceedings of the 17th IEEE/ACM International Symposium on Low-power Electronics and Design.Washington D.C.,USA:IEEE Press,2011:409-414. [13] ZHAO Guoliang.Research and implementation of 1024-point pipeline FFT algorithm based on FPGA[D].Xi'an:Xidian University,2011.(in Chinese)赵国亮.基于FPGA的1024点流水线结构FFT算法的研究与实现[D].西安:西安电子科技大学,2011. [14] FEI Yongzhou.Research and design of 12-bit high speed pipeline ADC[D].Nanjing:Southeast University,2017.(in Chinese)费永舟.12位高速流水线ADC的研究和设计[D].南京:东南大学,2017. [15] WU Ying.Application of DCT transform in image compression[J].Computer and Modernization,2013(4):103-106.(in Chinese)武瑛.DCT变换在图像压缩中的应用[J].计算机与现代化,2013(4):103-106. [16] XU Zhen.VLSI design of DCT/IDCT IP core based on image processing application[D].Wuhan:Huazhong University of Science and Technology,2004.(in Chinese)薛峥.基于图像处理应用的DCT/IDCT IP核的VLSI设计[D].武汉:华中科技大学,2004. |