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计算机工程 ›› 2011, Vol. 37 ›› Issue (21): 211-213. doi: 10.3969/j.issn.1000-3428.2011.21.072

• 工程应用技术与实现 • 上一篇    下一篇

适用于多核处理器的簇状片上网络设计

尤凯迪,肖瑞瑾,权 衡,虞志益   

  1. (复旦大学专用集成电路与系统国家重点实验室,上海 201203)
  • 收稿日期:2011-04-11 出版日期:2011-11-05 发布日期:2011-11-05
  • 作者简介:尤凯迪(1985-),男,硕士研究生,主研方向:片上网络,多核处理器设计;肖瑞瑾、权 衡,硕士研究生;虞志益,副教授
  • 基金资助:
    上海市科委集成电路专项基金资助项目(10706200300);复旦大学专用集成电路与系统国家重点实验室基金资助重点项目(09 ZD002)

Design of Clustered NoC for Multi-core Processor

YOU Kai-di, XIAO Rui-jin, QUAN Heng, YU Zhi-yi   

  1. (State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China)
  • Received:2011-04-11 Online:2011-11-05 Published:2011-11-05

摘要: 提出一种新型簇状片上网络架构。该架构以二维网状拓扑结构连接各个簇单元,每个簇单元由3个处理器、1个直接访存单元和1个簇共享存储单元组成。基于该架构的多核处理器可以获得更高的通信效率及存储器利用率。在实验系统上实现3 780点的快速傅里叶变换,结果表明,在快速傅里叶变换应用中存储器的利用率能提升至79.5%。

关键词: 片上网络, 多核处理器, 直接内存访问, 簇共享存储

Abstract: This paper presents a novel clustered Network-on-Chip(NoC) architecture for multi-core processor. The proposed architecture is a cluster array organized as a two-dimensional mesh. Each cluster includes three processors, one Direct Memory Access(DMA) and one cluster shared memory. The multi-core processor using such NoC architecture can obtain high communication efficiency and memory utilization ratio. It design a four-cluster prototype system and implement the 3 780-point Fast Fourier Transform(FFT) on it. In FFT application, the memory utilization ratio increases to 79.5%.

Key words: Network-on-Chip(NoC), multi-core processor, Direct Memory Access(DMA), cluster shared storage

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