计算机工程

• 体系结构与软件技术 • 上一篇    下一篇

重用感知的非一致缓存迁移策略研究

汪 玲,黄 炎,袁光辉   

  1. (安徽大学江淮学院计算机科学与电子技术系,合肥 230039)
  • 收稿日期:2012-11-30 出版日期:2014-02-15 发布日期:2014-02-13
  • 作者简介:汪 玲(1985-),女,讲师、硕士,主研方向:计算机体系结构,软件体系结构;黄 炎、袁光辉,助教
  • 基金项目:
    安徽省高校省级自然科学研究基金资助项目(KJ2013B012);安徽大学江淮学院科研基金资助项目(2011KJ0001)

Research on Reuse-aware Non-uniform Cache Migration Strategy

WANG Ling, HUANG Yan, YUAN Guang-hui   

  1. (Department of Computer Science and Electronic Technology, Jianghuai College, Anhui University, Hefei 230029, China)
  • Received:2012-11-30 Online:2014-02-15 Published:2014-02-13

摘要: 随着工艺的持续进步,多核处理器集成了越来越多的核以及片上缓存系统,因此利用非一致缓存架构(NUCA)应对片上多核处理器的缓存系统中逐渐增大的线延迟。高效的缓存块迁移策略对整个缓存系统至关重要。当前动态非一致缓存架构(D-NUCA)中的缓存块迁移策略未考虑缓存块的历史访问信息,导致缓存块在不同的bank之间抖动从而增加缓存块的访问延迟。为此,提出一种重用感知的缓存块迁移(RABM)策略,采用缓存块的历史迁移信息来预测将来的缓存块迁移,从而提升D-NUCA的性能以及降低整个缓存系统的功耗。基于PARSEC基准测试程序的全系统仿真结果显示,与D-NUCA相比,基于RABM的D-NUCA可以使每时钟周期指令数平均提高9.6%,片上缓存系统功耗降低14%。

关键词: 非一致缓存, 块迁移, 块查找, 重用感知, 多核处理器, 片上网络

Abstract: As technology scales down, more and more cores are integrated into single chip with larger and larger cache memories. Recently, Non-uniform Cache Architecture(NUCA) is proposed to mitigate the increasing wire delay for cache memories in multi-core systems. High performance block migration policy is crucial for the overall performance of the memory subsystem in multi-core systems. The block access information is not considered in the design of block migration strategy of Dynamic NUCA(D-NUCA) which can lead to the jitter of blocks among different cache banks, result in even longer access latency. Aiming at the lack of efficient block migration strategy, this paper proposes a Reuse-aware Block Migration(RABM) for D-NUCA. Through exploiting the historical block migration information as the hint, the proposed migration strategy can effectively improve the performance of D-NUCA and reduce caching system power consumption. Full system simulation result based on PARSEC benchmark test program show that D-NUCA based on RABM improves the Instruction per Cycle(IPC) by 9.6% on average, and reduces on-chip cache system power consumption by 14% on average compared with D-NUCA.

Key words: non-uniform cache, block migration, block lookup, reuse-aware, multi-core processor, Network on Chip(NoC)

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