基因算法加速器与芯片级进化研究

doi:10.3969/j.issn.1000-3428.2011.07.087

计算机工程 ›› 2011, Vol. 37 ›› Issue (7): 258-261. doi: 10.3969/j.issn.1000-3428.2011.07.087

基因算法加速器与芯片级进化研究

卜海祥¹，杨华秋¹，段欣¹，陈利光¹，来金梅¹，鲍丽春²

(1. 复旦大学专用集成电路与系统国家重点实验室，上海 201203；2. 北京航天飞控中心，北京 100094)

出版日期:2011-04-05 发布日期:2011-03-31
作者简介:卜海祥(1986－)，男，硕士，主研方向：可进化硬件；杨华秋、段欣，硕士；陈利光，博士后；来金梅，教授；鲍丽春，高级工程师
基金资助:
国家“863”计划基金资助项目(2007AA01Z285)；上海市科技创新行动计划集成电路设计专项基金资助项目“国产自主知识产权FPGA的产业化应用和深入研发”(08706200101)

Research on Genetic Algorithm Accelerator and On-chip Evolution

BU Hai-xiang ¹, YANG Hua-qiu ¹, DUAN Xin ¹, CHEN Li-guang ¹, LAI Jin-mei ¹, BAO Li-chun ²

(1. State Key Lab of ASIC & System, Fudan University, Shanghai 201203, China; 2. Beijing Aerospace Command and Control Center, Beijing 100094, China)

Online:2011-04-05 Published:2011-03-31

摘要/Abstract

摘要： 为改进芯片级进化速度，提出在可进化系统芯片FDP2009-2-SOPC中嵌入基因算法加速器的思想。采用硬件随机数方法优化芯片级进化中的基因算法，通过改变嵌入式CPU中的基因操作，优化芯片级进化流程。在包含基因算法加速器的可进化系统芯片FDP2009-2- SOPC上进行流片测试，结果表明，该基因算法加速器的性能及芯片级进化速度有较大提升。

关键词: 可进化硬件, 可进化系统芯片, 基因算法

Abstract: In order to improve the speed of on-chip evolution, this paper proposes an embedded accelerator of genetic algorithm in the evolvable system chip FDP2009-2-SOPC. It improves the implementation of genetic algorithm through hardware implementation of random number, and changes implementation of genetic operations in embedded CPU to improve the on-chip evolution flow. After the tape-out and verification of the evolvable system chip FDP2009-2-SOPC with the genetic algorithm accelerator, test results show that the performance of genetic algorithm accelerator and on-chip evolution speed are improved greatly.

Key words: Evolvable Hardware(EHW), evolvable system chip, genetic algorithm

中图分类号:

TP303

卜海祥, 杨华秋, 段欣, 陈利光, 来金梅, 鲍丽春. 基因算法加速器与芯片级进化研究[J]. 计算机工程, 2011, 37(7): 258-261.

BO Hai-Xiang, YANG Hua-Qiu, DUAN Xin, CHEN Li-Guang, LAI Jin-Mei, BAO Li-Chun. Research on Genetic Algorithm Accelerator and On-chip Evolution[J]. Computer Engineering, 2011, 37(7): 258-261.

http://www.ecice06.com/CN/Y2011/V37/I7/258

参考文献

[1] Garis H. Artificial Embryology: The Genetic Programming of an Artificial Embryo[M]//Soucek B. Dynamic, Genetic, and Chaotic Progra- mming. New York, USA: Wiley, 1992. [2] Lambert C, Kalganova T, Stomeo E. FPGA-based Systems for Evolvable Hardware[C]//Proc. of World Academy of Science, Engineering and Technology. Melbourne, Australia: [s. n.], 2006. [3] Hartmann M, Lehre K, Haddow P C. Evolved Digital Circuits and Genome Complexity[C]//Proc. of NASA/DoD Conf. on Evolvable Hardware. Washington D. C., USA: [s. n.], 2005. [4] 赵文红, 王宇平, 王巍. 快速寻优的全局优化进化算法[J]. 计算机工程, 2008, 34(8): 208-209. [5] Stomeo E, Kalganova T, Lambert C. Analysis of Genotype Size for an Evolvable Hardware System[C]//Proc. of World Academy of Science, Engineering and Technology. Stockholm, Sweden: [s. n.], 2005. [6] Movsovic K, Stomeo E, Kalganova T. Feasibility of the Evolu- tionary Algorithm Using Different Behaviours of the Mutation Rate to Design Simple Digital Logic Circuits[C]//Proc. of World Academy of Science, Engineering and Technology. Melbourne, Australia: [s. n.], 2006. [7] Higuchi T, Murakawa M. Evolvable Hardware at Function Level[C]//Proc. of IEEE Conf. on Evolutionary Computation. Indianapolis, USA: [s. n.], 1997. [8] Xinlinx Inc.. PLB IPIF[EB/OL]. (2006-02-02). http://www.xilinx. com/support/documentation/ip_documentation/ plb_ ipif.pdf. [9] 束礼宝, 宋克柱, 王砚方. 伪随机数发生器的FPGA实现与研究[J]. 电路与系统学报, 2003, 8(3): 121-126. [10] Duan Xin, Zhang Fanjiong, Lai Jinmei, et al. Design and Implementation of a Novel Platform-based SOPC Chip[C]//Proc. of Southern Conference on Programmable Logic Conf.. Ipojuca, Brazil: [s. n.], 2010. [11] Wang Liyun, Wang Yuan, Chen Liguang, et al. Uniform Routing Architecture for FPGA with Embedded IP Cores[C]//Proc. of ASICON’09. Changsha, China: [s. n.], 2009. [12] Hwang Keum-Sung, Cho Sung-Bae. Evolving Diverse Hardwares Using Speciated Genetic Algorithm[C]//Proc. of Congress on Evolutionary Computation. Hawaii, USA: [s. n.], 2002.

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