摘要： 给出一种改进的基-24频域抽取FFT算法，基于该算法和SDF结构，提出改进的多路基-24 FFT处理器结构，通过复用常复系数乘法器，减少硬件消耗并维持吞吐率不变。基于改进结构设计2路256点FFT处理器，在SMIC 0.13 μm工艺下综合、布局和布线后的版图核心面积为1.12 mm2，最高工作频率为100 MHz。

关键词: 快速傅里叶变换, 单路延迟反馈, 流水线, 基-24, 乘法器复用

Abstract: This paper proposes an improved radix-24 DIF Fast Fourier Transform(FFT) algorithm. On the basis of this algorithm and Single-path Delay Feedback(SDF) architecture, it proposes an improved multi-path radix-24 FFT processor architecture. It minimizes the number of general complex multiplier and the hardware cost can be reduced without sacrificing the throughout by sharing trivial complex multipliers. A two-path 256 points FFT processor adopting modified architecture is designed. The processor is synthesized, placed and routed using the SMIC 0.13 μm process with a layout core area of 1.12 mm2 and a max work frequency of 100 MHz.

Key words: Fast Fourier Transform(FFT), Single-path Delay Feedback(SDF), pipeline, radix-24, multiplier sharing

中图分类号: 

• TP303