Abstract: Aiming at the requirement that video decoder chips should be compatible with both AVS and H.264 video coding standard, a dual- mode variable length decoder is proposed. The reuse of barrel shifter and Exp-colomb decoder is adopted, and it uses combinational logic to look up table, optimizes and rebuilds code tables of AVS and H.264. The design is simulated and tested in ModelSim, synthesized and validated on the Field Programmable Gate Array(FPGA) chip. Result indicates that it can be applied to both AVS and H.264 standard, reduce the circuit size and complexity, and improve the efficiency of looking up table.

Key words: AVS standard, H.264 standard, variable length decoding, Field Programmable Gate Array(FPGA) chip, Exp-colomb code, Verilog Hardware Description Language(HDL)

摘要： 为使视频解码芯片能同时兼容AVS及H.264这2种视频编码标准，设计一种双模可变长解码器。该设计复用码流缓冲移位和指数哥伦布解码模块，采用组合逻辑电路查找码表，对AVS和H.264码表进行优化与重组。在ModelSim环境下完成仿真测试，并通过FPGA芯片进行综合验证。结果表明，该设计能有效支持AVS和H.264 2种标准，减小电路资源消耗和面积，并提高查找表的查找效率。

关键词: AVS标准, H.264标准, 可变长解码, 现场可编程门阵列芯片, 指数哥伦布码, Verilog硬件描述语言

CLC Number: 

• TN919