1 |
赵姗, 杨秋松, 李明树. 性能非对称多核处理器下异构感知调度技术. 软件学报, 2019, 30(4): 1164- 1190.
|
|
ZHAO S, YANG Q S, LI M S. Heterogenity-aware scheduling research on performance asymmetric multicore processors. Journal of Software, 2019, 30(4): 1164- 1190.
|
2 |
SADASIVAM S K, THOMPTO B W, KALLA R, et al. IBM Power9 processor architecture. IEEE Micro, 2017, 37(2): 40- 51.
doi: 10.1109/MM.2017.40
|
3 |
STONE H S. B70-4 theory of scheduling. IEEE Transactions on Computers, 1970, 19(9): 854- 855.
|
4 |
ROY P. Heuristic based task scheduling in multiprocessor systems with genetic algorithm by choosing the eligible processor. International Journal of Distributed and Parallel Systems, 2012, 3(4): 111- 121.
doi: 10.5121/ijdps.2012.3412
|
5 |
CHATTERJEE N, PAUL S, MUKHERJEE P, et al. Deadline and energy aware dynamic task mapping and scheduling for network-on-chip based multi-core platform. Journal of Systems Architecture, 2017, 74, 61- 77.
doi: 10.1016/j.sysarc.2017.01.008
|
6 |
GHARSELLAOUI H, KTATA I, KHARROUBI N, et al. Real-time reconfigurable scheduling of multiprocessor embedded systems using hybrid genetic based approach[C]//Proceedings of the 14th IEEE/ACIS International Conference on Computer and Information Science. Washington D. C., USA: IEEE Press, 2015: 15-22.
|
7 |
PAGANI S, KHDR H, CHEN J J, et al. Thermal Safe Power (TSP): efficient power budgeting for heterogeneous manycore systems in dark silicon. IEEE Transactions on Computers, 2017, 66(1): 147- 162.
doi: 10.1109/TC.2016.2564969
|
8 |
GAMATIÉ A, AN X, ZHANG Y, et al. Empirical model-based performance prediction for application mapping on multicore architectures. Journal of Systems Architecture, 2019, 98, 1- 16.
doi: 10.1016/j.sysarc.2019.06.001
|
9 |
VAZQUEZ R, EDUN A, GORDON-ROSS A, et al. Dynamic scheduling for heterogeneous multicores. SN Computer Science, 2021, 2(6): 486.
doi: 10.1007/s42979-021-00909-w
|
10 |
ESMAEILZADEH H, BLEM E, ST AMANT R, et al. Dark silicon and the end of multicore scaling. IEEE Micro, 2012, 32(3): 122- 134.
doi: 10.1109/MM.2012.17
|
11 |
NIKNAM S, PATHANIA A, PIMENTEL A D. T-TSP: transient-temperature based safe power budgeting in multi-/many-core processors[C]//Proceedings of the 39th IEEE International Conference on Computer Design. Washington D. C., USA: IEEE Press, 2021: 21-36.
|
12 |
FANG J, ZONG H, ZHAO H Y, et al. Intelligent mapping method for power consumption and delay optimization based on heterogeneous NoC platform. Electronics, 2019, 8(8): 912.
doi: 10.3390/electronics8080912
|
13 |
FANG J, ZHANG J X, LU S B, et al. Task scheduling strategy for heterogeneous multicore systems. IEEE Consumer Electronics Magazine, 2022, 11(1): 73- 79.
doi: 10.1109/MCE.2021.3073654
|
14 |
ISKANDAR V, SALAMA C, TAHER M. Dynamic thread mapping for power-efficient many-core systems under performance constraints. Microprocessors and Microsystems, 2022, 93, 104614.
doi: 10.1016/j.micpro.2022.104614
|
15 |
任良育, 赵成萍, 严华. 基于任务复制与冗余消除的多核调度算法. 计算机工程, 2019, 45(5): 59- 65.
URL
|
|
REN L Y, ZHAO C P, YAN H. Multi-core scheduling algorithm based on task duplication and redundancy elimination. Computer Engineering, 2019, 45(5): 59- 65.
URL
|
16 |
梁秋玲, 张向利, 张红梅, 等. 基于多核处理器的关联任务并行感知调度算法. 计算机工程, 2021, 47(7): 212- 217.
URL
|
|
LIANG Q L, ZHANG X L, ZHANG H M, et al. Parallel perceptual scheduling algorithm for related tasks based on multi-core processors. Computer Engineering, 2021, 47(7): 212- 217.
URL
|
17 |
QUAN W, PIMENTEL A D. A hybrid task mapping algorithm for heterogeneous MPSoCs. ACM Transactions on Embedded Computing Systems, 2015, 14(1): 1- 25.
|
18 |
TAKAI T, IWAMOTO H, TAKAMINE Y, et al. I. H. P. SAW technology and its application to microacoustic components (invited)[C]//Proceedings of IEEE International Ultrasonics Symposium. Washington D. C., USA: IEEE Press, 2017: 1-8.
|
19 |
RAPP M, SIKAL M B, KHDR H, et al. SmartBoost: lightweight ML-driven boosting for thermally-constrained many-core processors[C]//Proceedings of the 58th ACM/IEEE Design Automation Conference. Washington D. C., USA: IEEE Press, 2021: 11-19.
|
20 |
SHARMA Y, CHAKRABORTY S, MOULIK S. ETA-HP: an energy and temperature-aware real-time scheduler for heterogeneous platforms. The Journal of Supercomputing, 2022, 78(8): 1- 25.
|
21 |
MATHIYAZHAGAN S, SIRISHA MAGANTI L. Thermal management of multi core processor using U configured parallel microchannel cooling system. Journal of Physics: Conference Series, 2022, 2178(1): 012006.
doi: 10.1088/1742-6596/2178/1/012006
|
22 |
SHARMA Y, MOULIK S. HEAT: a heterogeneous multicore real-time scheduler with efficient energy and temperature management. ACM SIGAPP Applied Computing Review, 2022, 22(2): 34- 43.
doi: 10.1145/3558053.3558056
|
23 |
KIM Y G, KIM M, KONG J, et al. An adaptive thermal management framework for heterogeneous multi-core processors. IEEE Transactions on Computers, 2020, 69(6): 894- 906.
doi: 10.1109/TC.2020.2970062
|
24 |
|
25 |
PRICOPI M, MUTHUKARUPPAN T S, VENKATARAMANI V, et al. Power-performance modeling on asymmetric multi-cores[C]//Proceedings of International Conference on Compilers, Architecture and Synthesis for Embedded Systems. Washington D. C., USA: IEEE Press, 2013: 18-25.
|
26 |
NEMIROVSKY D, ARKOSE T, MARKOVIC N, et al. A machine learning approach for performance prediction and scheduling on heterogeneous CPUs[C]//Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing. Washington D. C., USA: IEEE Press, 2017: 14-26.
|
27 |
NEMIROVSKY D, ARKOSE T, MARKOVIC N, et al. A general guide to applying machine learning to computer architecture. Supercomputing Frontiers and Innovations, 2018, 5(1): 95- 115.
|
28 |
PATHANIA A, HENKEL J. HotSniper: sniper-based toolchain for many-core thermal simulations in open systems. IEEE Embedded Systems Letters, 2019, 11(2): 54- 57.
doi: 10.1109/LES.2018.2866594
|
29 |
AL SHALABI L, SHAABAN Z, KASASBEH B. Data mining: a preprocessing engine. Journal of Computer Science, 2006, 2(9): 735- 739.
doi: 10.3844/jcssp.2006.735.739
|
30 |
KIM Y, PAPAMICHAEL M, MUTLU O, et al. Thread cluster memory scheduling: exploiting differences in memory access behavior[C]//Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture. Washington D. C., USA: IEEE Press, 2010: 77-89.
|
31 |
WILLIAMS S, WATERMAN A, PATTERSON D. Roofline: an insightful visual performance model for floating-point programs and multicore architectures. Office of Entific & Technical Information Technical Reports, 2009, 52(4): 65- 76.
|
32 |
HUANG W, GHOSH S, VELUSAMY S, et al. HotSpot: a compact thermal modeling methodology for early-stage VLSI design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006, 14(5): 501- 513.
doi: 10.1109/TVLSI.2006.876103
|
33 |
ANSARI M, SAFARI S, YEGANEH-KHAKSAR A, et al. Peak power management to meet thermal design power in fault-tolerant embedded systems. IEEE Transactions on Parallel and Distributed Systems, 2019, 30(1): 161- 173.
doi: 10.1109/TPDS.2018.2858816
|
34 |
MARKOVIC N, NEMIROVSKY D, MILUTINOVIC V, et al. Hardware round-robin scheduler for single-ISA asymmetric multi-core[C]//Proceedings of European Conference on Parallel Processing. Berlin, Germany: Springer, 2015: 122-134.
|
35 |
BIENIA C, KUMAR S, LI K. PARSEC vs. SPLASH-2: a quantitative comparison of two multithreaded benchmark suites on chip-multiprocessors[C]//Proceedings of IEEE International Symposium on Workload Characterization. Washington D. C., USA: IEEE Press, 2008: 47-56.
|