基于芯粒的多核处理器目录控制器的敏捷验证

doi:10.19678/j.issn.1000-3428.0070593

计算机工程 ›› 2026, Vol. 52 ›› Issue (8): 176-183. doi: 10.19678/j.issn.1000-3428.0070593

基于芯粒的多核处理器目录控制器的敏捷验证

罗莉¹^,²^,*(), 冯权友¹^,², 周理¹^,², 铁俊波¹^,², 龚锐¹^,², 潘国腾¹^,²

1. 国防科技大学计算机学院, 湖南长沙 410073
2. 先进微处理器芯片与系统重点实验室, 湖南长沙 410073

收稿日期:2024-11-07 修回日期:2025-02-24 出版日期:2026-08-15 发布日期:2025-04-17
通讯作者: 罗莉
作者简介:
罗莉(CCF会员)，女，研究员、博士，主研方向为高性能计算机体系结构、高性能通用微处理器设计与验证
冯权友，副研究员、博士
周理，助理研究员、博士
铁俊波，副研究员、博士
龚锐，副研究员、博士
潘国腾，副研究员、博士
基金资助:
国家自然科学基金青年基金项目(62203457); 并行与分布式处理国防科技重点实验室开放基金(WDZC20235250112)

Agile Verification of Directory Control Unit for Chiplet-based Multi-core Processors

LUO Li¹^,²^,*(), FENG Quanyou¹^,², ZHOU Li¹^,², TIE Junbo¹^,², GONG Rui¹^,², PAN Guoteng¹^,²

1. College of Computer Science, National University of Defense Technology, Changsha 410073, Hunan, China
2. Key Laboratory of Advanced Microprocessor Chips and Systems, Changsha 410073, Hunan, China

Received:2024-11-07 Revised:2025-02-24 Online:2026-08-15 Published:2025-04-17
Contact: LUO Li

摘要/Abstract

摘要：

芯粒已成为芯片设计的新趋势, 随着微处理器结构向多核化、众核化发展, 高速缓冲存储器(Cache)一致性协议也日趋复杂。在多芯粒集成的微处理器中, Cache一致性协议的验证更是一个具有重要应用价值的技术问题。基于目录的Cache协议是最广泛应用的硬件实现方法, 针对自主研发的分布式目录控制器(DCU), 研究多芯粒集成的处理器目录控制器的敏捷验证技术, 随机测试采用否定选择算法(NSA)的优化机制。实验结果表明: 随机测试激励减少40%的条件下, 功能覆盖率较未使用否定选择算法的随机测试提高了28百分点; 随机测试激励和定向测试激励相结合, 功能覆盖率最终达到100%。同时设计一致性检查器, 监视一致性协议事务的生命周期, 用于快速定位设计错误, 追踪问题的精确场景。实践中, 该检查器定位的协议错误占设计错误的90%, 有效提高了验证效率和验证质量。

关键词: 芯粒, 高速缓冲存储器一致性协议, 分布式目录控制器, 否定选择算法, 敏捷验证

Abstract:

Chiplets have emerged as a new trend in chip design. With the evolution of microprocessor architectures toward multi-core and many-core implementations, the complexity of Cache coherence protocols has increased substantially. For microprocessors integrating multiple chiplets, the verification of Cache coherence protocols is a technically critical issue with significant practical value. The directory-based Cache coherence protocol is the most widely adopted hardware-implementation approach. Focusing on a self-developed distributed Directory Controller Unit (DCU), this study investigates agile verification technologies for DCU in multi-chiplet integrated processors. An optimized mechanism based on a Negative Selection Algorithm (NSA) is employed in random testing, where functional coverage was improved by 28 percentage points under a 40% reduction in random test stimuli. By combining random and directed test stimuli, the functional coverage ultimately reaches 100%. Additionally, a coherence checker is designed to monitor the entire lifecycle of the coherence protocol transactions. This enables the rapid localization of design errors and accurate tracing of problematic scenarios, with 90% of the design bugs successfully identified. This approach effectively enhances verification efficiency and quality.

Key words: chiplets, Cache coherence protocol, distributed Directory Control Unit (DCU), Negative Selection Algorithm (NSA), agile verification

罗莉, 冯权友, 周理, 铁俊波, 龚锐, 潘国腾. 基于芯粒的多核处理器目录控制器的敏捷验证[J]. 计算机工程, 2026, 52(8): 176-183.

LUO Li, FENG Quanyou, ZHOU Li, TIE Junbo, GONG Rui, PAN Guoteng. Agile Verification of Directory Control Unit for Chiplet-based Multi-core Processors[J]. Computer Engineering, 2026, 52(8): 176-183.

https://www.ecice06.com/CN/Y2026/V52/I8/176

图/表 11

图1 Die：16核SoC芯粒结构

Fig.1 Die: 16-core SoC chiplet structure

图2 多芯粒集成32核、64核处理器示意图

Fig.2 Schematic diagram of multi-chiplet integrated 32/64-core processor

图3 跨芯粒的读操作协议流程

Fig.3 Cross-chiplet read operation protocol flow

图4 跨芯粒写操作协议流程

Fig.4 Cross-chiplet write operation protocol flow

图5 DCU目录项entry的定义

Fig.5 Definition of a directory entry in DCU

图6 多芯粒集成的处理器的目录控制器敏捷验证环境

Fig.6 Agile verification environment for the DCU in a multi-chiplet integrated processor

图7 一个抗体Gen实例

Fig.7 An example of antibody Gen

图8 抗体种群表示的测试向量

Fig.8 test antibody population

图9 随机测试激励执行的功能覆盖率

Fig.9 The functional coverage status of random test

图10 设计错误分布率

Fig.10 Design bugs rate

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