基于芯粒的多核处理器目录控制器的敏捷验证

doi:10.19678/j.issn.1000-3428.0070593

摘要/Abstract

摘要： 芯粒已成为芯片设计的新趋势，随着微处理器结构向多核化、众核化发展，Cache一致性协议也日趋复杂。多芯粒集成的微处理器中，Cache一致性协议的验证更是一个具有重要应用价值的技术问题。基于目录的Cache协议是最广泛应用的硬件实现方法，本文针对自主研发的分布式目录控制器，研究了多芯粒集成的处理器目录控制器的敏捷验证技术，随机测试采用否定选择免疫算法的优化机制，随机测试激励减少40%的条件下，功能覆盖率提高了28%；随机测试激励和定向测试激励相结合，功能覆盖率最终达到100%；同时还设计了一致性检查器，监视一致性协议事务的生命周期，可以快速定位设计错误，追踪问题的精确场景，定位设计错误占90%，有效提高了验证效率和验证质量。

Abstract: core configurations, cache coherence protocols are becoming increasingly complex. The verification of cache coherence protocols for chiplet-based microprocessors is of significant value. The directory is the most widely used circuits for implementing hardware coherence. This paper focuses on the agile verification of directory controllers for multi-core processors based on chiplets. By adopting an optimized random testing approach based on the negative selection algorithm, we achieved a 28% increase in functional coverage while reducing random test stimuli by 40%. By combining random and directed test stimulus, we ultimately achieved 100% functional coverage. Furthermore, we designed a coherence checker that monitors the lifecycle of coherence transactions flows. This tool enables rapid identification of design bugs, precise trace of transaction scenarios, and localization of 90% protocol bugs. Overall, these efforts have significantly improved both the efficiency and quality of the verification process.

罗莉, 冯权友, 周理, 铁俊波, 龚锐, 潘国腾. 基于芯粒的多核处理器目录控制器的敏捷验证[J]. 计算机工程, doi: 10.19678/j.issn.1000-3428.0070593.

LUO Li, FENG Quanyou, ZHOU Li , TIE Junbo, GONG Rui, PAN Guoteng. Agile Verification of Directory-based Cache Coherency for Multi-core Processors in Chiplets Era[J]. Computer Engineering, doi: 10.19678/j.issn.1000-3428.0070593.

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