摘要： 提出了一种低功耗的综合BIST方案。该方案是采取了屏蔽无效测试模式生成、提高应用测试向量之间的相关性以及并行加载向量等综合手段来控制测试应用，使得测试时测试向量的输入跳变显著降低，从而大幅度降低芯片的测试功耗。测试实验表明，该方案既能减少测试应用时间，又能够有效地降低芯片测试功耗，平均输入跳变仅为类似方案的2.7%。

关键词: SoC芯片, 内建自测试, 低功耗

Abstract: This paper presentes a low-power synthesis BIST scheme. The scheme adopts some synthesis measures that deletes the void or redundancy testing patterns and increases the relativity of the test vectors and parallel loaded test vectors, so that the power consumption inside the circuit under testing is reduced enormously. This scheme not only decreases testing-time, but also reduces testing-power effectively. The average input switching activity is only 2.7% of the similar type scheme.

Key words: SoC chip, BIST, Low-power

中图分类号: 

• TP 391