参考文献
[1]Tullsen D M,Eggers S J,Levy H M.Simultaneous Multithreading:Maximizing On-chip Parallelism[J].ACM SIGARCH Computer Architecture News,1995,23(2):392-403.
[2]Cazorla F J,Ramirez A,Valero M,et al.Optimising Long-latency-load-aware Fetch Policies for SMT Processors[J].International Journal of High Perfor-mance Computing and Networking,2004,2(1):45-54.
[3]Eyerman S,Ecckhout L.A Memory-level Parallelism Aware Fetch Policy for SMT Processors[C]//Proceedings of the 13th IEEE International Symposium on High Performance Computer Architecture.Washington D.C.,USA:IEEE Press,2007:240-249.
[4]Weng Lichen,Liu Chen.A Resource Utilization Based Instruction Fetch Policy for SMT Processors[J].Microprocessors and Microsystems,2015,39(1):1-10.
[5]孙彩霞,张民选.基于多个取指优先级的同时多线程处理器取指策略[J].电子学报,2006,34(5):790-795.
[6]Cazorla F J,Ramirez A,Valero M,et al.Dynamically Controlled Resource Allocation in SMT Processors[C]//Proceedings of the 37th International Symposium on Micro-architecture.Washington D.C.,USA:IEEE Press,2004:171-182.
[7]Choi S,Yeung D.Learning-based SMT Processor Resource Distribution via Hill-climbing[J].ACM SIGARCH Computer Architecture News,2006,34(2):239-251.
[8]Tullsen D M,Eggers S J,Emer J S,et al.Exploiting Choice:Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor[J].ACM SIGARCH Computer Architecture News,1996,24(2):191.
[9]Tullsen D M,Brown J A.Handling Long-latency Loads in a Simultaneous Multithreading Processor[C]//Pro-ceedings of the 34th Annual ACM/IEEE International Symposium on Microarchitecture.Washington D.C.,USA:IEEE Computer
Society,2001:318-327.
[10]El-Moursy A,Albonesi D H.Front-end Policies for Improved Issue Efficiency in SMT Processors[C]//Proceedings of the 9th International Symposium on High-performance Computer Architecture.Washington D.C.,USA:IEEE Press,2003:31-40.
[11]Cazorla F J,Ramirez A,Valero M,et al.DCache Warn:An I-Fetch Policy to Increase SMT Efficiency[C]//Proceedings of the 18th International Parallel and Distributed Processing Symposium.Washington D.C.,USA:IEEE Press,2004:74.
[12]孙彩霞,张民选.DWarn+:一种改进的同时多线程处理器取指策略[J].小型微型计算机系统,2007,28(9):1720-1723.
[13]Liu Yannan,Chen Tianzhou,Zhang Tiefei,et al.Dealing with the Functional Units Starvation in SMT[C]//Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & the 9th IEEE
International Conference on Embedded Software and Systems.Washington D.C.,USA:IEEE Press,2012:208-215.
[14]Wang Huaping,Koren I,Krishna C M.An Adaptive Resource Partitioning Algorithm in SMT Processors[C]//Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques.New York,USA:ACM
Press,2008:230-239.
[15]Henning J L.SPEC CPU2000:Measuring CPU Performance in the New Millennium[J].Computer,2000,33(7):28-35.
[16]Luo Kun,Gummaraju J,Franklin M.Balancing Throughput and Fairness in SMT Processor[C]//Proceedings of 2001 IEEE International Symposium on Performance Analysis of Systems and Software.Washington D.C.,USA:IEEE Press,2001:164-171.
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