摘要： 在级综合的基础上,提出了在级进行电路可测性检查和改进方法。与一般的可测性分析方法不同,该文不是基于对电路VHDL RTRT的可控制性和可观察性的量化分析,而是通过检查和改进可测性不佳的局部设计,使得整体电路的可测性得到提升,达到高故障覆盖率。

关键词: 可测性设计, 可测性综合, 寄存器传输级, VHDL

Abstract: This paper presents a VHDL RT-level testability check and improvement method. By modifying parts of circuit structure with bad testability and detecting combinational loops in the design, the overall circuit becomes highly testable,thus high fault coverage is also obtained.

中图分类号: 

• TN402