摘要： 介绍了一种大容量、高速率数据采集器技术，解释了80位输入数据到16位数据输出的地址映射表及地址计数器的概念，并用CPLD技术和VHDL硬件语言来实现这些功能。

关键词: CPLD, VHDL语言, 数据采集

Abstract: This paper intrduces the technologies of a large capacity and high speed data collector, and explains the ideas of a list of address mapping of 80 bits input data to 16 bits output data and an address increaser,which are realized by CPLD technology and VHDL hardware language.

中图分类号: 

• TP274.2