摘要： 介绍了使用VHDL描述有限状态机的方法，重点分析了综合过程中的难点并提供了解决方法。最后以乘法电路为例实现了可综合的FSM描述并通过门级仿真验证正确性。

关键词: VHDL, 有限状态机, 综合, 乘法电路

Abstract: The approach of description of finite state machine with VHDL is presented. This paper analyses the emphasises in the process of synthesis and provides the solutions. At last, it implements a synthetical multiplication circuit with VHDL and method presented, the function of it is proved correctly through logic simulation.

中图分类号: 

• TN402