摘要： 提出了i386体系结构支持的底层进程硬件模型。并给出了它的扩展模型及实现算法,以突破信息网络在硬件平台限制的条件下对进程最大数量的约束,有效解决新一代信息网络系统随机产生的大量并发进程进行海量通信的基本技术问题以及在通用计算机体系结构硬设计时必须考虑的问题。

关键词: 进程, 进程切换, 主体, 客体, 进程硬件上下文

Abstract: This paper proposes a bottom process hardware model sustained by i386 architecture, presents the scalable model and implements algorithms. The aim is to breach the information network restriction on the process maximum restricted by hardware platform, and effectively resolve the basic technical problem of vast communications required by mass intercurrent process random produced by new information network system.

中图分类号: 

• TP302