摘要: 讨论了3种常用的浮点加法算法,并在VirtexII系列FPGA上实现了LOP算法。实验结果表明在FPGA上可以实现快速浮点加法器,最高速度可达152MHz,资源占用也在合理的范围内。
关键词:
浮点加法器,
移位器,
前导1预测,
FPGA
Abstract: Three commonly used Floating-point addition algorithms are discussed, and the LOP algorithm is implemented on VirtexII seriesFPGA. The implementing results show that the fast floating-point adder can be implemented on FPGA, the highest running frequency is 152MHzand the area cost is rational compare to the entire resources.
中图分类号:
郭天天,张志勇,卢焕章. 快速浮点加法器的FPGA实现[J]. , 2005, 31(16): 212-214.
GUO Tiantian, ZHANG Zhiyong, LU Huanzhang. FPGA Implementation of Fast Floating-point Adder[J]. , 2005, 31(16): 212-214.