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›› 2005, Vol. 31 ›› Issue (16): 212-214.

• 论文 • 上一篇    下一篇

快速浮点加法器的FPGA实现

郭天天,张志勇,卢焕章   

  1. 国防科技大学ATR实验室,国防科技大学ATR实验室,国防科技大学ATR实验室 长沙 410073
  • 发布日期:2005-08-25

FPGA Implementation of Fast Floating-point Adder

GUO Tiantian, ZHANG Zhiyong, LU Huanzhang   

  1. (ATR Lab, NUDT, Changsha 410073)
  • Published:2005-08-25

摘要: 讨论了3种常用的浮点加法算法,并在VirtexII系列FPGA上实现了LOP算法。实验结果表明在FPGA上可以实现快速浮点加法器,最高速度可达152MHz,资源占用也在合理的范围内。

关键词: 浮点加法器, 移位器, 前导1预测, FPGA

Abstract: Three commonly used Floating-point addition algorithms are discussed, and the LOP algorithm is implemented on VirtexII seriesFPGA. The implementing results show that the fast floating-point adder can be implemented on FPGA, the highest running frequency is 152MHzand the area cost is rational compare to the entire resources.

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