摘要： 提出了一种为不支持调试模式的CPU 扩展调试功能的系统设计方法。该方法在保持原CPU 结构性和完整性的情况下，在片上增加了CPU 监视/运行分析模块、调试控制模块、时钟/复位管理和JTAG 兼容的调试访问接口，用较少的硬件开销实现了指令/数据断点、单步、运行/停止、CPU 复位、查看CPU 核心寄存器、读取/修改外部存储器以及在线编程等功能，且调试命令的设置和执行完全独立于CPU，保证了CPU 运行的实时性。
关键词:
调试模式；片上调试系统；门控时钟；JTAG
Abstract: A design of on-chip debug facilities for a CPU not supporting debug mode is introduced. It preserves structural integrity of the CPU by utilizing some add-on units including CPU monitor, debug control, clock/reset management and a JTAG compatible debug access port to implement all the higher level debug functions with only a small hardware overhead. The debug command configuration and execution are totally independent of the CPU so that the CPU can run in real time
Key words:
Debug mode; On-chip debug system; Gated clock; JTAG
赵 岩，张果，张春，王志华. 一种扩展的片上实时调试系统设计[J]. 计算机工程, 2006, 32(8): 283-285.
ZHAO Yan, ZHANG Guo, ZHANG Chun, WANG Zhihua. Design of An Extended On-chip Real Time Debug System[J]. Computer Engineering, 2006, 32(8): 283-285.