一种加速访存地址计算的编译优化

doi:10.19678/j.issn.1000-3428.0062878

摘要/Abstract

摘要： 在国产申威高性能多核服务器系统中，基础编译系统对应用程序中访存操作进行代码生成时，没有考虑国产处理器指令特征，导致编译器生成的访存地址计算代码效率较低，影响国产高性能处理器的性能。为充分发挥国产处理器高性能计算能力，提出一种加速访存地址计算的编译优化方法。加速访存地址计算编译优化基于处理器支持带扩展因子的运算指令，在编译器后端内存地址表达式合法性检查中，添加针对乘加模式的地址计算表达式合法性检查算法，自动识别地址表达式中存在的乘加运算并进行合法性检验，对符合条件的地址表达式在代码生成阶段匹配生成带扩展因子的运算指令来快速计算访存地址，从而加快访存指令的发射与执行以及应用程序中的访存地址生成，提升访存效率。使用行业标准性能测试集SPEC CPU2006对优化效果进行评测，结果表明，相比优化前SPECspeed Integer与SPECspeed Float Point两个子集，该优化方法平均性能分别提高了2.53%与1.50%。

关键词: 精简指令集计算机, 地址计算, 代码生成, 编译优化, 多核处理器

Abstract: In domestic Sunway high-performance multi-core server systems, when the basic compilation system generates the code for access operation in the application program, the instructional characteristics of the domestic processor are not considered.As a result, the access address calculation code generated by the compiler is inefficient, which hinders the performance of the high-performance processor.To fully realize the high-performance computing capabilities of domestic processors, a compiler optimization method is proposed to accelerate the computation of access addresses.The compiler optimization of accelerated access address computation is based on the processor's support of operational instructions using an extension factor.During the compiler back-end memory address expression validity check, an address calculation expression validity check algorithm for multiply-add mode is added.The algorithm automatically recognizes the multiplicative operation in the address expression and verifies its validity.It then generates operational instructions using the extension factor to calculate the access address quickly in the code generation stage, which accelerates the launch and execution of the access instructions.The optimization method can significantly speed up the generation of the access address in the application and improve access efficiency.The method is automatically implemented by the compiler and is transparent to the program developer.Experimental results show that the average performances of the two subsets of SPECspeed Integer and SPECspeed Float Point are improved by 2.53% and 1.50%, respectively, as compared with that prior to optimization.

Key words: Reduced Instruction Set Computer(RICS), address calculation, code generation, compiler optimization, multicore processors

中图分类号:

TP391

高秀武, 姜军, 白书敬, 黄亮明. 一种加速访存地址计算的编译优化[J]. 计算机工程, 2023, 49(1): 173-180.

GAO Xiuwu, JIANG Jun, BAI Shujing, HUANG Liangming. A Compiler Optimization for Accelerating Access Address Calculation[J]. Computer Engineering, 2023, 49(1): 173-180.

https://www.ecice06.com/CN/Y2023/V49/I1/173

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