计算机工程 ›› 2012, Vol. 38 ›› Issue (3): 276-279,283.doi: 10.3969/j.issn.1000-3428.2012.03.091

• 开发研究与设计技术 • 上一篇    下一篇

面向可重构计算系统的模块映射算法

刘 杰,吴 强,赵全伟   

  1. (湖南大学信息科学与工程学院, 长沙 410082)
  • 收稿日期:2011-07-30 出版日期:2012-02-05 发布日期:2012-02-05
  • 作者简介:刘 杰(1985-),男,硕士研究生,主研方向:可重构计算;吴 强,副教授、博士;赵全伟,硕士研究生
  • 基金项目:
    国家“863”计划基金资助项目(2007AA01Z104);湖南省自然科学基金资助项目(07JJ6136);中央高校基本科研业务费基金资助项目

Module Mapping Algorithm for Reconfigurable Computing System

LIU Jie, WU Qiang, ZHAO Quan-wei   

  1. (College of Information Science and Engineering, Hunan University, Changsha 410082, China)
  • Received:2011-07-30 Online:2012-02-05 Published:2012-02-05

摘要: 为消除重构时间对可重构计算系统性能的影响,针对多重构模块,提出一种基于动态部分可重构技术的顺序型应用程序模块映射算法。利用动态可重构技术的高效性和灵活性,通过隐藏重构时间,达到减少程序执行时间和提高系统性能的目的。基于JPEG编码测试实例的实验结果表明,运用该算法实现的模块映射方案其程序执行速度是软件实现方式的3.31倍,是硬件方式的2.59倍。

关键词: 可重构计算, 模块映射算法, 动态部分可重构, 重构时间, 现场可编程门阵列

Abstract: In order to reduce the impact of the configuration time to the performance of reconfigurable computing, this paper proposes a module mapping algorithm based on dynamic partial reconfigurable technology for sequential applications. It deals with the mapping of multi-modules. It utilizes the high effectiveness and flexibility of dynamic reconfiguration to hide the configuration time, so that the program execution time can be reduced and the system performance is improved. Experiment based on JPEG encoding example shows that the algorithm achieves 3.31 and 2.59 speedups compared to implementation methods of pure software and pure hardware respectively.

Key words: reconfigurable computing, module mapping algorithm, dynamic partial reconfigurable, configuration time, Field Programmable Gate Array(FPGA)

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