基于FPGA模拟的阻变神经网络加速器评估方法

doi:10.19678/j.issn.1000-3428.0059988

摘要/Abstract

摘要： 基于阻变器件的存算一体神经网络加速器需在架构设计初期进行仿真评估，确保神经网络精度符合设计要求，但传统阻变神经网络加速器的软件模拟器运行速度较慢，难以应对大规模网络的架构评估需求。为加快仿真评估速度，设计一种基于现场可编程门阵列（FPGA）模拟的阻变神经网络加速器评估方法，分析现有阻变神经网络加速器的架构通用性，利用FPGA资源的高度并行性和运行时指令驱动的灵活模拟方式，通过硬件资源的分时复用实现多层次存算一体架构和指令集的功能模拟及主流神经网络的快速性能评估。实验结果表明，针对不同规模的忆阻器阵列和深度神经网络，该评估方法相比MNSIM和DNN NeuroSim软件模拟器运行速度分别提升了40.0~252.9倍和194.7~234.2倍。

关键词: 神经网络加速器, 存算一体, 现场可编程门阵列, 忆阻器, 模拟器, 深度神经网络

Abstract: The Processing-in-Memory(PIM) neural network accelerators based on resistive devices require careful simulation and evaluation during the early stage of architecture design, which ensures the accuracy of neural networks to meet the requirements of design.However, the software emulator for traditional resistive neural network accelerators is limited in the speed, which makes it hard to meet the evaluation requirements of large-scale network architectures.To accelerate simulation and evaluation, this paper proposes an evaluation method based on Field Programmable Gate Array(FPGA) emulation for resistive neural network accelerators.The method is constructed based on the analysis of the generalization performance of the existing resistive neural network accelerators.Then by using the high parallelism and the flexible emulation approaches driven by runtime instructions of FPGA, time-sharing is performed on hardware resources to simulate a multi-level PIM architecture and the functions of an instruction set.On this basis, the performance of mainstream neural networks can be evaluated rapidly.Experimental results show that for different sizes of memristor array and Deep Neural Network(DNN), the evaluation method provides a 40.0~252.9 times speedup compared with the MNSIM simulator, and 194.7~234.2 times speedup compared with the DNN NeuroSim simulator.

Key words: neural network accelerator, Processing-in-Memory(PIM), Field Programmable Gate Array(FPGA), memristor, emulator, Deep Neural Network(DNN)

中图分类号:

TP368.1

石永泉, 景乃锋. 基于FPGA模拟的阻变神经网络加速器评估方法[J]. 计算机工程, 2021, 47(12): 209-214.

SHI Yongquan, JING Naifeng. Evaluation Method Based on FPGA Emulation for Resistive Neural Network Accelerators[J]. Computer Engineering, 2021, 47(12): 209-214.

https://www.ecice06.com/CN/Y2021/V47/I12/209

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