计算机工程 ›› 2012, Vol. 38 ›› Issue (5): 251-254.doi: 10.3969/j.issn.1000-3428.2012.05.078

• 工程应用技术与实现 • 上一篇    下一篇

基于FPGA的浮点向量协处理器设计

韩正飞1,李劲松2,潘红兵1,李 丽1,沙 金1,何书专1   

  1. (1. 南京大学微电子设计研究所,南京 210093;2. 合肥工业大学微电子设计研究所,合肥 230009)
  • 收稿日期:2011-05-27 出版日期:2012-03-05 发布日期:2012-03-05
  • 作者简介:韩正飞(1987-),男,硕士研究生,主研方向:多核处理器;李劲松,硕士研究生;潘红兵,副教授;李 丽,教授;沙 金,副教授;何书专,工程师
  • 基金项目:
    国家“863”计划基金资助项目(2008AA01Z135);国家自然科学基金资助项目(60876017);江苏省科技厅科技支撑计划基 金资助项目(BE2009143)

Design of Floating-point Vector Coprocessor Based on FPGA

HAN Zheng-fei 1, LI Jin-song 2, PAN Hong-bing 1, LI Li 1, SHA Jin 1, HE Shu-zhuan 1   

  1. (1. Institute of VLSI Design, Nanjing University, Nanjing 210093, China; 2. Institute of VLSI Design, Hefei University of Technology, Hefei 230009, China)
  • Received:2011-05-27 Online:2012-03-05 Published:2012-03-05

摘要: 为满足现代数字信号处理中大量数据的运算需求,利用ARM946和Xilinx公司的现场可编程门阵列芯片逻辑资源和IP库,设计专门用于浮点复数向量运算的64位协处理器,对相关浮点运算进行优化,并在硬件仿真平台上进行测试。结果表明,该协处理器可使浮点复数向量运算性能得到大幅提高。

关键词: 现场可编程门阵列, 浮点复数向量, 协处理器, 批处理

Abstract: To meet the requirement of a series of complex data processing in modern Digital Signal Processor(DSP), a 64 bit floating-point coprocessor specially for floating-point complex vector arithmetic is proposed with the logic resources and IP library of ARM9 and the Field Programmable Gate Array(FPGA) chip from Xilinx. The algorithm of related floating-point arithmetic could be revised. Results of the test on the hardware simulation platform show that the floating-point complex vector arithmetic performance is greatly improved by the coprocessor.

Key words: Field Programmable Gate Array(FPGA), floating-point plural vector, coprocessor, batch processing

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