计算机工程 ›› 2012, Vol. 38 ›› Issue (23): 240-242,246.doi: 10.3969/j.issn.1000-3428.2012.23.059

• 工程应用技术与实现 • 上一篇    下一篇

精简指令集计算机协处理器设计

李辉楷,韩 军,翁新钎,贺中柱,曾晓洋   

  1. (复旦大学专用集成电路与系统国家重点实验室,上海 201203)
  • 收稿日期:2012-03-05 出版日期:2012-12-05 发布日期:2012-12-03
  • 作者简介:李辉楷(1986-),男,硕士研究生,主研方向:专用数字集成电路设计,片上系统;韩 军,助理研究员;翁新钎、贺中柱,硕士研究生;曾晓洋,教授、博士生导师
  • 基金项目:
    国家自然科学基金资助项目(61176023)

Design of RISC Coprocessor

LI Hui-kai, HAN Jun, WENG Xin-qian, HE Zhong-zhu, ZENG Xiao-yang   

  1. (State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China)
  • Received:2012-03-05 Online:2012-12-05 Published:2012-12-03

摘要: 针对AES与SHA-3候选算法中Gr?stl软件运算速度慢的问题,提出一种通过精简指令集计算机(RISC)协处理器来加速算法运算的设计方案。该协处理器复用片上高速缓存充当查找表来加速运算,并在RISC处理器的基本指令集架构中增加特殊指令。实验结果表明,与传统基于并行查找表的方案相比,该方案能够以较小的硬件代价加速AES与Gr?stl运算。

关键词: 精简指令集计算机, 协处理器, 高速缓存, 并行表查找, 寄存器堆, 指令集架构

Abstract: Aiming at the slow operating speed of existing AES and SHA-3 candidates Gr?stl algorithm, this paper presents a design scheme for algorithm acceleration using Reduced Instruction Set Computer(RISC) coprocessor. Data cache is multiplexed as look-up table by the coprocessor for acceleration. Several specific instructions are added to the RISC instruction set architecture to accelerate the operation. Experimental results show that the scheme can reduce hardware cost compared with the implementation using traditional parallel on-chip look-up.

Key words: Reduced Instruction Set Computer(RISC), coprocessor, cache, Parallel Table Look Up(PTLU), Register File(RF), Instruction Set Architecture(ISA)

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